Clock recovery circuit for QAM demodulator

Details Clock recovery circuit for QAM demodulator Clock recovery circuit for QAM demodulator

1997-03-07

1998-08-04

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

331 1A, 329304, 329310, 375261, 375344, 375376, H03D 300, H03L 7085, H04L 2734, H04L 2738

Patent

active

057899886

ABSTRACT:
In a clock recovery circuit in a demodulator of a multi-level quadrature amplitude modulation (QAM) system, an analog/digital (A/D) converter performs an A/D conversion upon a coherent-detected baseband analog signal in synchronization with a sampling clock signal having a time period half of a symbol time period. An phase detector receives successive first, second and third sampled data from the A/D converter, determines whether or not a signal transition formed by the first and second sampled data crosses a zero value within a predetermined time deviation, and compares a polarity of the second sampled data with a polarity of one of the first and second sampled data to generate a phase detection signal. Further, a loop filter is connected to an output of the phase detector, and a voltage controlled oscillator supplies the sampling clock signal to the A/D converter in accordance with an output signal of the loop filter.

REFERENCES:
patent: 5042052 (1991-08-01), Roberts et al.
patent: 5608764 (1997-03-01), Sugita et al.
S. Otani et al., "Development of a Variable-Rate Digital Modem for Satellite Communication Systems", NEC Res. & Develop., No. 92, pp. 25-31, Jan. 1989.

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