Clock recovery circuit for burst communications systems

Details Clock recovery circuit for burst communications systems Clock recovery circuit for burst communications systems

1980-09-02

1982-07-13

Safourek, Benedict V.

Multiplex communications

Wide area network

Packet switching

370103, 375107, H04L 700, H04J 306, H04J 600

Patent

active

043398170

ABSTRACT:
A clock recovery circuit includes an oscillator having a frequency which is substantially equal to the clock frequency of bursts which are transmitted from a plurality of stations. A phase difference detector circuit responds to phase differences between clock signals extracted from each of the bursts and from the output from the oscillator. An averaging circuit averages the detected phase differences over an interval which is designated by a first control signal. A memory circuit stores the averaged phase difference in response to a second control signal and reads out the stored phase differences in response to a third control signal. A control circuit generates the first to third control signals in response to the output from the oscillator. A phase shift circuit shifts the phase of the output from the oscillator, based on the phase difference read out from the memory circuit. This generates and recovers the original clock pulse signal. The clock of the first burst corresponding to the stored phase difference is used as the clock for a second burst from the same station which transmits the first burst.

REFERENCES:
patent: 3676599 (1972-07-01), Heetman
patent: 3940558 (1976-02-01), Gabbard et al.
"The Design of a PSK Modem for the Telesat TDMA System", S. Yokoyama et al. (Nippon Electric Co. Ltd., Japan) pp. 44-11 to 44-15.
"Communications Satellite Systems"-J. Martin; Time-Division Multiple Access, pp. 243-246.

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