Clock recovery circuit employing delay-and-difference circuit an

Details Clock recovery circuit employing delay-and-difference circuit an Clock recovery circuit employing delay-and-difference circuit an

1995-07-27

1997-12-30

Bocure, Tesfaldet

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

375376, H04L 700

Patent

active

057039143

ABSTRACT:
A clock recovery circuit receives an input signal having an eye pattern and takes differences at certain intervals to generate a differential signal. A set of comparators detect timings at which the differential signal matches different levels, and generate pulse signals at these timings. A gate-signal generating circuit detects timing relationships among these pulse signals, and activates a gate signal when pulse sequences having certain timing relationships are detected. A delay circuit delays one of the pulse signals to create a delayed signal. A gate circuit outputs the delayed signal as a timing signal when the gate signal is active. A phase-locked loop generates a clock signal synchronized to the timing signal.

REFERENCES:
patent: 3878475 (1975-04-01), Okano et al.
patent: 5416805 (1995-05-01), Tonello et al.
patent: 5448201 (1995-09-01), Kawabata
Nakamura, Iguchi, and Kodama, U.S. Patent Application Serial No. 08/307,632, filed Sep. 20, 1994 on the basis of an earlier International Application designating the U.S.
Akaiwa & Nagata, "A Linear Modulation Method for Digital Mobile Radio Communication", Institute of Electronics & Communication Engineers of Japan, 1985, No. 2384.
Mobuta et al, ".pi./4-shift QPSK Differential Demodulator for Digital Cordless Telephone," Spring 1992 Meeting of Institute of Electronics, Communication & Information Engineers,B-344.
Matsumoto et al, "A study on Clock Recovery Circuit for .pi./4-shift QPSK Signals," 1993 Spring Meeting of Institute of Electronics, Communication & Information Engineers of Japan, B-317.

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