Clock recovery circuit and receiver using same

Details Clock recovery circuit and receiver using same Clock recovery circuit and receiver using same

1994-12-20

1997-09-23

Chin, Stephen

Pulse or digital communications

Synchronizers

Self-synchronizing signal

375360, 370518, 327291, H04L 702

Patent

active

056712588

ABSTRACT:
A receiver for NRZ data does not require a separate transmission media for the clock. Rather, a clock recovery circuit is included in the receiver capable of recovering the clock based on transitions detected in the NRZ data alone. The clock recovery circuit comprises an edge detection circuit which receives the data stream and generates edge detection signals indicating transitions in the data stream. Reference clock generation circuity generates a plurality of reference clock signals shifted in phase with respect to one another. Phase quantizing circuitry is responsive to the edge detection signals and the plurality of reference clock signals. The phase quantizing circuitry generates a quantization signal indicating one of the plurality of reference clock signals having a particular phase relationship to the edge detection signals. Clock selection circuitry, having inputs coupled to the plurality of reference clock signals and an output, is responsive to the quantization signal to select the indicated reference clock as the recovered clock signal for the data stream. The reference clock generation circuity includes a local clock input to receive a local clock, and a reference generator which is responsive to the local clock to generate a first reference wave and a second reference wave one quarter cycle out of phase relative to the first reference wave. A plurality of reference clock generators generate respective reference clock signals in response to the first and second reference waves, each of the reference clock generators generating a reference clock signal having a phase determined by relative amplitudes of the first and second reference waves.

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M. Bazes, et al., "A Novel CMOS Digital Clock and Data Decoder", IEEE Journal of Solid-State Circuits, vol. 27, No. 12, pp. 1934-1940, Dec. 1992 .

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