Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
2007-11-27
2007-11-27
Fan, Chieh M. (Department: 2611)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C375S371000, C375S238000, C331S034000, C331S057000, C331S010000, C365S233100, C716S030000
Reexamination Certificate
active
10653919
ABSTRACT:
A clock recovery circuit includes a phase discriminating circuit for discriminating, at every edge of a received data signal, phase lead or phase lag of an identically directed edge of the clock signal, and outputting the phase discrimination signal; an edge detecting circuit for detecting edges of the received data signal, outputting an edge detection signal of a fixed pulse width, delaying the received data signal and outputting the delayed signal; an exclusive-OR gate for outputting, as an edge injection signal, an exclusive-OR signal between the phase discrimination signal and delayed signal; and a voltage-controlled oscillator for variably controlling frequency of ring oscillation, injecting the edge injection signal into the loop of ring oscillation, and outputting a clock signal locked to the received data signal.
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Kaeriyama Shunichi
Mizuno Masayuki
Fan Chieh M.
McGinn IP Law Group PLLC
Pathak Sudhanshu C.
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