Clock recovery circuit and communication device

Details Clock recovery circuit and communication device Clock recovery circuit and communication device

2006-01-17

2006-01-17

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Regenerating or restoring rectangular or pulse waveform

C375S355000

Reexamination Certificate

active

06987410

ABSTRACT:
A clock recovery circuit includes plural stages of first variable delay elements for sequentially delaying a data signal by a first delay amount, plural stages of second variable delay elements for sequentially delaying a clock signal by a second delay amount which is larger than the first delay amount, a plurality of timing comparators for sampling a plurality of the data signals delayed by the plural stages of first variable delay elements with the clock signal delayed by the second variable delay elements of the same stages, a plurality of EOR circuits for performing exclusive OR operation on a pair of sampling results by a pair of the sequential timing comparators, and a recovery variable delay circuit for delaying the clock signal based on the operation result of the plurality of EOR circuits.

REFERENCES:
patent: 5430773 (1995-07-01), Marbot
patent: 5590154 (1996-12-01), Forni et al.
patent: 6757327 (2004-06-01), Fiedler
patent: 5-110550 (1993-04-01), None
patent: 9-224020 (1997-08-01), None
patent: 11-88310 (1999-03-01), None
patent: WO 03/036796 (2003-05-01), None
Patent Abstracts of Japan publication No. 09-224020, publication dated Aug. 26, 1997 (1 page).
Patent Abstracts of Japan publication No. 11-088310, publication date Mar. 30, 1999 (1 page).
Patent Abstracts of Japan publication No. 05-110550, publication date Apr. 30, 1993 (1 page).

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