Clock recovery circuit

Details Clock recovery circuit Clock recovery circuit

1998-09-16

2001-08-14

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

C327S161000, C713S401000

Reexamination Certificate

active

06275547

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a clock recovery circuit and, more particularly, to a clock recovery circuit for shortening data and clock synchronization time.
BACKGROUND OF THE INVENTION
In order to perform burst-mode transition in the prior art, use is made of a clock recovery circuit for generating a clock that is accurately synchronized to data. A clock recovery circuit for such burst-mode transmission according to the prior art will be described with reference to
FIG. 6
, which is a block diagram illustrating the conventional clock recovery circuit.
The clock recovery circuit depicted in
FIG. 6
is disclosed in Electronics Letters, Nov. 5, 1992, Vol.28, No 23, pp. 2127-2129. As shown in
FIG. 6
, the clock recovery circuit comprises a delay circuit (Delay)
305
to which data
301
is input; a gate-input controlled oscillator (GVCO)
307
to which the data
301
is input; an inverter
315
for inverting the data
301
, which is input thereto; a gate-input controlled oscillator (GVCO)
309
to which the inverted data output by the inverter
315
is input; a multiplexing circuit (MUX)
308
for combining the outputs of the gate-input controlled oscillators
307
,
309
and outputting the resulting signal as an extracted clock; a data-type flip-flop (referred as a “D-F/F” below)
306
having a data terminal to which the extracted clock
303
output by the multiplexing circuit
308
is input, whereby the delayed data
301
output by the delay circuit
305
is latched and output as reproduced data
302
; a phase detecting circuit (PD)
311
to which a reference clock
304
is input; and a loop filter (LF)/charge pump (CP)
312
to which a signal output by the phase detecting circuit
311
is input and from which an output signal is delivered to the gate-input controlled oscillators
307
,
309
and to a gate-input controlled oscillator (GVCO)
310
, the latter delivering its output signal to the phase detecting circuit
311
based upon the signal output by the loop filter/charge pump
312
.
The phase detecting circuit
311
, loop filter/charge pump
312
and gate-input controlled oscillator
310
in this clock recovery circuit construct a phase-locked loop (referred to as a “PLL” below).
Thus, the clock recovery circuit shown in
FIG. 6
is constituted by a PLL the basic components of which are the single loop filter/charge pump
312
, the single phase detecting circuit
311
, the single multiplexing circuit
308
, the single delay circuit
305
, the single D-F/F
306
serving as a latch circuit, and the three gate-input controlled oscillators
307
,
309
,
310
.
The operation of the conventional clock recovery circuit shown in
FIG. 6
will now be described.
In terms of the connections, an ordinary PLL is constructed by the loop filter/charge pump
312
, phase detecting circuit
311
and one gate-input controlled oscillator
310
. The reference clock
304
is input to the phase detecting circuit
311
, which becomes synchronized to the reference clock
304
and delivers its output to the loop filter/charge pump
312
. The output signal from the loop filter/charge pump
312
enters the gate-input controlled oscillators
307
,
309
and
310
. Accordingly, the outputs of the gate-input controlled oscillators
307
and
309
are synchronized to the reference clock
304
at all times.
The timings of the various signals associated with the conventional clock recovery circuit shown in
FIG. 6
will be described with reference to
FIG. 7
, which is a timing chart illustrating these signals.
As shown in
FIG. 7
, the gate-input controlled oscillator
307
outputs a clock A in conformity with the rising edge of the data
301
and the gate-input controlled oscillator
309
outputs a clock B in conformity with the falling edge of the data
301
. The two clocks A and B are multiplexed by the multiplexing circuit
308
, whereby the extracted clock
303
is produced. Further, owing to the input of the extracted clock
303
to the its data terminal, the D-F/F
306
latches the data
301
that has passed through the delay circuit
305
and generates the reproduced data
302
. As a result, the extracted clock
303
synchronized to the data and the reproduced data
302
can be obtained with the clock recovery circuit according to the prior art illustrated in FIG.
6
.
Further, a clock recovery circuit employing a similar technique using the data
301
instead of the reference clock
304
has been disclosed in the 1996 Symposium on VLSI Circuits Digest of Technical Papers, pp. 122-123.
SUMMARY OF THE DISCLOSURE
A problem with the conventional clock recovery circuits is that it is required that the single gate-input controlled oscillator
307
and single gate-input controlled oscillator
309
in the PLL be held in the synchronized state. As a result, it is required that the system wait for several dozen clock pulses or more until the synchronized state is obtained. This makes it difficult shorten synchronization time.
Accordingly, an object of the present invention is to provide a clock recovery circuit in which it is possible to shorten the time needed to obtain synchronization.
Further objects of the present invention will become apparent in the entire disclosure.
According to a first aspect of the present invention, the foregoing object is attained by providing a clock recovery circuit comprising: a first synchronous delay circuit (generally termed as “synchronous multi-step delay circuit”), to which a reference clock and data are input, for outputting a first clock; an inverter for inverting the data and then outputting inverted data; a second synchronous delay circuit, to which the reference clock and the inverted data that is output by the inverter are input, for outputting a second clock; a delay circuit, to which the data is input, for outputting this input data upon delaying it; a pulse combining circuit, to which the first clock output by the first synchronous delay circuit and the second clock output by the second synchronous circuit are input, for combining these input clocks and outputting the result as an extracted clock; and a data-type flip-flop, having a data terminal to which the extracted clock output by the pulse combining circuit is input, in response to which the data-type flip-flop latches the data that has been delayed in the delay circuit and outputs the latched data as reproduced data.
The first synchronous delay circuit has (1) a first delay line, to which the reference clock is input, made up by at least one first individual delay circuit; (2) a first selection circuit array made up by at least one second individual selection circuit to which the reference clock output by a respective one of the first individual delay circuits making up the first delay line is input and which is rendered conductive based upon the data (to provide a first generated reference clock); and (3) a first NAND gate, to which the data and the (first generated) reference clock that is output by the first selection circuit array are input, for outputting a first clock.
The second synchronous delay circuit has (1) a second delay line, to which the reference clock is input, made up by at least one third individual delay circuit; (2) a second selection circuit array made up by at least one fourth individual selection circuit to which the reference clock output by a respective one of the third individual delay circuits making up the second delay line is input and which is rendered conductive based upon the inverted data (to provide a second generated reference clock); and (3) a second NAND gate, to which the data inverted by the inverter and the (second generated) reference clock that is output by the second selection circuit array are input, for outputting a second clock.
In accordance with the first aspect of the present invention, therefore, the reference clock is delayed by being input to the first delay line of the first synchronous delay circuit. By inputting the data to the first selection circuit array of the first synchronous delay circuit, the delayed reference clock is

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