Clock recovery circuit

Details Clock recovery circuit Clock recovery circuit

1984-06-11

1987-03-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307474, 328 63, 328 72, 375120, H03D 324, H04L 2534

Patent

active

046510265

ABSTRACT:
The invention provides a clock recovery circuit for deriving a recovered clock signal from the band limited multi-level digital signal. The multi-level digital signal is compared with a number of reference levels in a bank of comparators whose outputs are combined to provide a marking signal indicative of threshold crossings by the multi-level signal. The marking signal consists of groups of transition markers separated by eye intervals. A signal source provides clock pulses and window pulses with the window pulses being synchronized with the eye intervals to provide a recovered clock signal.
The invention may be implemented entirely in digital form and is particularly suitable for use in partial response signalling in which band limited multi-level digital signals are transmitted without additional clock signals. Performance may be further enhanced by utilizing a smoothing phase locked loop to provide a smoothed clock signal.

REFERENCES:
patent: 4339823 (1982-07-01), Predina et al.

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