Clock recovery circuit

Details Clock recovery circuit Clock recovery circuit

1987-01-20

1988-05-10

Griffin, Robert L.

Pulse or digital communications

Spread spectrum

Direct sequence

375 86, 329 50, H03D 324

Patent

active

047440961

ABSTRACT:
A clock recovery circuit having two inputs (Vx, Vy) for receiving the in-phase and quadrature paths respectively from a demodulator, said clock recovery circuit comprising a first module (30) which includes a phase lock loop (15) and provides an output having a spectrum line at the clock frequency, said clock recovery circuit further comprising two second clock recovery modules (31, 32), each second clock recovery module having a first input (33, 34) connected to a respective one of the two demodulated paths (Vx, Vy) and a second input (35, 36) connected to the output from the first module (30), each of said second modules comprising, in succession from said first input, a sampled threshold device (37, 38, 39, 40) for providing the sign of the signal conveyed by the corresponding path and the sign of the error, and which may be made use of by circuits for performing signal regeneration per se, a phase estimator circuit (41, 42), a filter circuit (43, 44), and a voltage controlled phase shifter circuit (45, 46) controlled by the voltage output from the filter circuit and connected to shift the phase of the signal applied to the second input (35, 36) prior to its application to the threshold circuit.

REFERENCES:
patent: 4054838 (1977-10-01), Tretter
patent: 4105975 (1978-08-01), Sanders et al.
patent: 4394626 (1983-07-01), Kurihara et al.
patent: 4419759 (1983-12-01), Poklemba
patent: 4458356 (1984-07-01), Toy
patent: 4648100 (1987-03-01), Mardirosian
IEEE Transactions on Communications; vol. COM-24, No. 5, May 1976, pp. 516-531, New York; K. H. Mueller et al; "Timing Recovery in Digital Synchronous Data Receivers".

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