Clock recovery circuit

Details Clock recovery circuit Clock recovery circuit

2006-04-17

2009-11-10

Wang, Ted M (Department: 2611)

Pulse or digital communications

Receivers

Angle modulation

C375S376000, C375S373000, C375S360000, C375S327000

Reexamination Certificate

active

07616708

ABSTRACT:
A clock recovery circuit comprising an initial delay select circuit, a delay locked loop and a clock synthesizer circuit is provided. The initial delay select circuit comprises an initial timing generator, a first multiplexer and an initial value generator. The delay locked loop comprises a delay chain, a phase detector, a counter, and a decoder circuit. The delay locked loop delays an input clock signal to generate a first delay signal and several unit delay signals. The initial value generator receives the unit delay signals to generate an initial value used as an initial counting value of the delay locked loop to prevent harmonic lock. The delay locked loop controls the phase difference between the input clock signal and the first delay signal. The output clock signal of the clock recovery circuit is generated by the clock synthesizer circuit based on the input clock signal and the first delay signal.

REFERENCES:
patent: 5173617 (1992-12-01), Alsup et al.
patent: 5663665 (1997-09-01), Wang et al.
patent: 6137325 (2000-10-01), Miller, Jr.
patent: 6281726 (2001-08-01), Miller, Jr.
patent: 6750688 (2004-06-01), Takai
patent: 6862015 (2005-03-01), Fujioka et al.

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