Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
2007-07-10
2007-07-10
Phu, Phuong (Department: 2611)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C375S371000, C375S375000, C375S376000, C331S057000, C327S144000
Reexamination Certificate
active
10458428
ABSTRACT:
The clock recovery circuit includes a first oscillator and an edge detector. The first oscillator generates a plurality of clocks having different phases and a predetermined frequency. The edge detector detects two clocks, among the plurality of clocks, between edges of which an input data signal has made a transition. The first oscillator includes a plurality of delay cells connected in a ring, and outputs of the plurality of delay cells are output as the plurality of clocks. Each of the plurality of delay cells selectively delays a first-delay added input data signal or the signal output from the preceding delay cell, and outputs the selected delayed signal. The edge detector controls one delay cell among the plurality of delay cells corresponding to the result of the detection, to delay and output the first-delay added input data signal.
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“156 Mbps CMOS Clock Recovery Circuit for Burst-mode Transmission”, Makoto Nakamura, et al., 1996 Symposium on VLSI Circuits Digest of Technical Papers, pp. 122-123.
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