Clock recovery circuit

Details Clock recovery circuit Clock recovery circuit

2006-11-14

2006-11-14

Corrielus, Jean B (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S356000, C375S357000, C375S358000

Reexamination Certificate

active

07136441

ABSTRACT:
A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

REFERENCES:
patent: 5493571 (1996-02-01), Engdahl et al.
patent: 5570370 (1996-10-01), Lin
patent: 5670913 (1997-09-01), Garcia Palancar
patent: 5889828 (1999-03-01), Miyashita et al.
patent: 6040742 (2000-03-01), Bailey et al.
patent: 6064248 (2000-05-01), Seki
patent: 6229362 (2001-05-01), Choi
patent: 6236696 (2001-05-01), Aoki et al.
patent: 6466634 (2002-10-01), O'Toole et al.
patent: 6643787 (2003-11-01), Zerbe et al.
patent: 6763060 (2004-07-01), Knapp
patent: 5-126357 (1981-10-01), None
patent: 61-70830 (1986-04-01), None
patent: 5-136635 (1993-06-01), None
patent: 8-237117 (1996-09-01), None
patent: 10-327068 (1998-12-01), None
patent: 11-122232 (1999-04-01), None
patent: 11-215112 (1999-08-01), None
patent: 11-243327 (1999-09-01), None
D.H. Wolaver, “Phase-Locked Loop Circuit Design”, Section 10-2, pp. 213-216, Prentice Hall (1991).
R. Gu, et al., “A 0.5-3.5Gb/s Low-Power Low-Jitter Serial Data CMOS Transceiver”, ISSCC Digest of Technical Papers, pp. 352-353, Feb. 1999.

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