Clock recovery circuit

Details Clock recovery circuit Clock recovery circuit

2005-07-05

2005-07-05

Ha, Dac V. (Department: 2634)

Pulse or digital communications

Receivers

Angle modulation

C375S355000, C370S503000, C348S537000

Reexamination Certificate

active

06914945

ABSTRACT:
In a clock recovery circuit for DTV using a VSB modulation method, if the frequency of the symbol clock is fs, since the frequency difference between the fs/2 component signal of the VSB signal and the pilot signal is constant at fs/2, it is possible accurately to detect the phase error from their differential signal. Furthermore there is no distortion of the clock signal frequency of the VSB signal, even when the symbol data is distorted by multi-pass distortion or the like, since clock signal regeneration is performed by frequency domain processing. By employing this type of principle and performing phase error detection for each symbol at a time, it is possible to ensure a high speed tracking performance for clock signal regeneration.

REFERENCES:
patent: 5787123 (1998-07-01), Okada et al.
patent: 5802461 (1998-09-01), Gatherer
patent: 5859671 (1999-01-01), Kim
patent: 5872815 (1999-02-01), Strolle et al.
patent: 6445423 (2002-09-01), Bouillet et al.
patent: 63-211935 (1988-09-01), None
patent: 63-290049 (1988-11-01), None
patent: 8-70332 (1996-03-01), None
patent: 10-84396 (1998-03-01), None
patent: 2000-49882 (2000-02-01), None
Gary Sgrignoli et al., “VSB Modulation Used For Terrestrial and Cable Broadcasts”, IEEE Transactions on Consumer Electronics, vol. 41, No. 3, Aug. 1995, pp. 367-382.

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