Clock recovery circuit

Details Clock recovery circuit Clock recovery circuit

2000-12-01

2004-09-28

Deppe, Betsy L. (Department: 2634)

Pulse or digital communications

Synchronizers

Self-synchronizing signal

C375S373000, C375S376000

Reexamination Certificate

active

06798857

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to clock recovery circuits, in particular circuits for recovering a clock from serial digital data.
Serial data is sent on a number of transmission mediums without a separate clock signal for clocking the data and determining when one period ends and the next begins. This requires that the receiver circuitry be able to recover the clock from the data itself. Examples of clock recovery circuits can be found in U.S. Pat. Nos. 6,035,409; 6,100,765; and 6,101,230.
One of the issues involved in clock recovery is maintaining the clock phase aligned with incoming data. This can be particularly problematic where there are stretches of data without a transition in the data for the clock recovery circuit to key on. It would be desirable to provide a clock recovery circuit which provides the above functions, can be implemented without much circuitry, and can be implemented in digital circuitry.
SUMMARY OF THE INVENTION
The present invention provides a clock recovery circuit which has a transition detector connected to the incoming data stream. An output of the transition detector is connected to a gate, such as a D flip-flop, which has an input receiving the recovered clock. A zero or one output will be generated depending upon whether the transition is before or after the rising edge of the recovered clock. An accumulator circuit accumulates a count for each transition, providing the results to a comparison circuit. The comparison circuit compares the accumulated count to maximum and minimum thresholds, and provides advance or retard outputs when those thresholds are exceeded. A phase circuit adjusts the phase of the recovered clock by advancing or retarding it after a sufficient number of transitions have been detected either in advance or behind the recovered clock to justify such an adjustment.
The invention can be implemented in simple digital circuitry, and can use an accumulator circuit which need only store six or fewer bits. With four bits, a value of +/−7 can be stored, which is sufficient for most purposes.
In one embodiment the accumulator is clocked by the transition as well, insuring that only transitions accumulate in the accumulator. The flip-flop output is preferably connected to the select input of a multiplexer, with the inputs being either positive or negative 1. Thus, either a positive or negative 1 will be provided to the accumulator, to accumulate up or down upon that corresponding transition. Advance and retard outputs of the comparison circuit are connected through an OR gate back to a reset input of the accumulator.
The present invention provides a clock recovery circuit that works in periods of no data. It also provides a circuit that is simple, can be implemented with digital circuitry, and does not require much chip space, and only uses a small accumulator.
For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 4584695 (1986-04-01), Wong et al.
patent: 5012198 (1991-04-01), Okada et al.
patent: 5040193 (1991-08-01), Leonowich et al.
patent: 5463351 (1995-10-01), Marko et al.
patent: 5598448 (1997-01-01), Girardeau, Jr.
patent: 5754606 (1998-05-01), Matsuyama et al.
patent: 6064236 (2000-05-01), Kuwata et al.
patent: 6584163 (2003-06-01), Myers et al.

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