Clock recovery circuit

Details Clock recovery circuit Clock recovery circuit

1999-01-14

2001-10-23

Bocure, Tesfaldet (Department: 2731)

Pulse or digital communications

Synchronizers

Self-synchronizing signal

C375S350000

Reexamination Certificate

active

06307904

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a clock recovery circuit, and more particularly for such a circuit for use in an asynchronous, fixed rate data communication system.
BACKGROUND OF THE INVENTION
In an asynchronous, fixed rate data communication system, data is transmitted at a predetermined fixed clock frequency and is received at a receiver which must have the same predetermined clock in order to recover the transmitted data. The clock at the receiver must thus be synchronised with the clock at the transmitter.
Usually, due to the limited size of the communication channel, or bandwidth, the data information and the transmitter clock information are combined and transmitted together. The receiver must then recover the clock information in order to synchronise with the transmitter.
Conventionally, the receiver includes a clock recovery circuit that uses a receiver clock having a frequency which is higher by an integral multiple N than the transmitter clock, and an edge detector to detect edges of a signal transmitted by the transmitter. A state sequencer having N states is reset by each detected edge and the output of the state sequencer provides a recovered clock signal which must be synchronised with the transmitter clock.
Although such a recovered clock signal is reasonably accurate, a problem occurs when an edge of the receiver clock and an edge of the incoming signal arrive simultaneously at the edge detector. when this occurs, an instability arises and the edge detector can provide its output either correctly or one clock pulse later. If the edge detector output is incorrect, the counter will be incorrectly reset and the recovered clock signal will also be incorrect, causing potential problems with data recovery.
BRIEF SUMMARY OF THE INVENTION
The present invention therefore seeks to provide a clock recovery circuit which overcomes, or at least reduces the above-mentioned problems of the prior art.
Accordingly, in one aspect, the invention provides a clock recovery circuit comprising: a clock information edge detector comprising: a digital signal input; and an edge detect signal output; a state sequencer comprising: a clock signal input; a current state signal output; a state reset signal input; and a recovered clock information signal output; and a state corrector comprising: an edge detect signal input coupled to the edge detect signal output of the clock information edge detector; a current state signal input coupled to the current state signal output of the state sequencer; and a state reset signal output coupled to the state reset signal input of the state sequencer.
In another aspect the present invention provides a method for recovering a clock signal comprising the steps of: receiving a clock signal and a digital signal which includes clock information edges, wherein the clock signal has an integral multiple N higher frequency than that of the digital signal; stepping through a predetermined sequence of N states in accordance with the clock signal; providing a current state signal indicating a current state; detecting a clock information edge in the digital signal; counting the number of states since the detection of the last clock information edge; determining whether the current state is one of a plurality of predetermined allowable states; comparing the number of states counted with N; resetting a state sequencer to an earlier state than the current state when the number of states counted is greater than N; resetting the state sequencer to a later state than the current state when the number of states counted is less than N; and generating a recovered clock information signal in accordance with at least part of the current state signal.


REFERENCES:
patent: 4355398 (1982-10-01), Cook
patent: 4737971 (1988-04-01), Lanzafame et al.
patent: 5297869 (1994-03-01), Benham
patent: 5696800 (1997-12-01), Berger

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