Clock recovery circuit

Details Clock recovery circuit Clock recovery circuit

1998-08-10

2001-10-02

Chin, Stephen (Department: 2734)

Pulse or digital communications

Synchronizers

Frequency or phase control using synchronizing signal

C375S371000, C375S373000, C375S374000, C375S375000, C375S376000

Reexamination Certificate

active

06298104

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a clock recovery circuit. More particularly this invention relates to a clock recovery circuit which enables synchronous period of data and clock to be shortened.
DESCRIPTION OF THE RELATED ART
FIG. 1
is a circuit diagram showing a conventional example of a clock recovery circuit for implementing burst transmission. As disclosed by “ELECTRONICS LETTER Nov. 5, 1992 Vol. 28 No. 23 pp. 2127-2129”, the clock recovery circuit of
FIG. 1
has a basic configuration which comprises a phase-locked loop (PLL) including a pair of a loop filter LF and a charge pump CP, a phase detector PD, a multiplexer MUX, a delay circuit Delay, a latched-circuit D-F/F, three sets of gate input voltage-controlled oscillator GVCO.
In the clock recovery circuit as shown in
FIG. 1
, the ordinary PLL consists of the loop filter LF, the charge pump CP, the phase detector PD, and the set of gate input voltage-controlled oscillator GVCO. The clock recovery circuit of
FIG. 1
causes the signal to be synchronized with the reference clock
304
by way of input, the signal from the loop filter, at this time, is inputted to remaining two sets of the gate input voltage-controlled oscillator GVCO, thus synchronized state is always maintained to the reference clock
304
. Further as shown in
FIG. 2
, the clocks A, and B which transmit in answer to either leading edge or trailing edge of the data
301
respectively are multiplexed by the multiplexer MUX to generate the clock
303
. The latched-circuit D-F/F which causes data
301
through the delay circuit Delay to be latched, generates regenerative data
302
.
Further, there is the method disclosed in “1996 Symposium on VLSI Circuits Digest of Technical Papers pp. 122-123”, which method utilizes the data
301
in stead of the reference clock
304
similar to the conventional method described above.
However, in the conventional circuit, it is necessary to maintain one set of gate voltage-controlled oscillator GVCO of the synchronized state in the phase locked-loop (PLL), thus it should be waited for the time period for expending more than scores of clocks until the synchronized state is obtained.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention to provide a clock recovery circuit which enables the necessary time for reaching synchronized state to be shortened.
In one arrangement to be described below by way of example in illustration of the invention, a clock recovery circuit includes a synchronous delay circuit which sets a delay time equivalent to a minimum data pitch of an input data, the minimum data pitch of input data being the time necessary to propagate the smallest element of input data, and which maintains the delay time, a pulse synthesis circuit which generates a clock from a data edge with a pulse from the synchronous delay circuit as an input, and a latched-circuit which latches data by using the clock from the pulse synthesis circuit, thus generating regenerative data.
In one particular arrangement to be described in illustration of the present invention, by way of example, there is provided a synchronous delay circuit which sets a delay time equivalent to a minimum data pitch of data from both edges of the input data.
In one yet particular arrangement to be described in illustration of the present invention, by way of example, there is provided a synchronous delay circuit which sets a delay time equivalent to a minimum data pitch of data from two successive input data.
In another particular arrangement to be described in illustration of the present invention, by way of example, there is provided a delay time set by the synchronous delay circuit which delay time is equivalent to width of 1-bit of the data.
In another arrangement to be described below in illustration of the present invention there is provided a data processing method of a clock recovery circuit which consists of a synchronous delay circuit, a pulse synthesis circuit, and a latched-circuit comprises the steps of setting a delay time equivalent to a minimum data pitch of an input data, and maintaining the delay time, generating a clock from a data edge with a pulse from the synchronous delay circuit as an input, and latching data by using the clock from the pulse synthesis circuit, thus generating regenerative data.
The above and further objects and novel features of the invention will be more fully understood from the following detailed description when the same is read in connection with the accompanying drawings. It should be expressly understood, however, that the drawings are for purpose of illustration only and are not intended as a definition of the limits of the invention.


REFERENCES:
patent: 5127026 (1992-06-01), Kelly et al.
patent: 5455540 (1995-10-01), Williams
patent: 5566204 (1996-10-01), Kardontchik et al.
patent: 5579352 (1996-11-01), Liewellyn
patent: 5696800 (1997-12-01), Berger
patent: 5878097 (1999-03-01), Hase et al.
patent: 8-204524 (1996-08-01), None
patent: 8-330949 (1996-12-01), None
M. Banu and A. E. Dunlop; Electronics Letter Nov. 5, 1992 vol. No.: 23 pp. 2127-2129.
Makoto Nakamura, Noboru Ishihara, and Yukio Akazawa 1996 Symposium on VLSI Circuits Digest of Technical Papers pp. 122-123.

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