Clock recovery circuit

Details Clock recovery circuit Clock recovery circuit

1989-09-21

1991-02-26

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328164, 328 63, 307139, 375118, H03K 508, H04D 900

Patent

active

049964445

ABSTRACT:
A clock recovery circuit includes a resonant circuit which is driven into oscillation at a clock frequency by binary 1 pulses in a data signal supplied thereto, a clock signal being derived from the resonant circuit via a buffer and a limiting amplifier. The resonant circuit has a high Q to accommodate long sequences of binary Os during which it is not driven. In order to prevent over-driving when the data signal has a high density of binary 1s, a level detector detects when the oscillation amplitude exceeds a threshold level, whereupon a flip-flop is set to control a gate to inhibit driving of the resonant circuit until its oscillation amplitude has decayed. The flip-flop is clocked by the data signal to operate in synchronism with the incoming data, and may be followed by a second similarly clocked flip-flop to avoid potential errors.

REFERENCES:
patent: 3304505 (1967-02-01), Pricer
patent: 4298986 (1981-11-01), Hughes
patent: 4679252 (1987-07-01), Holland
patent: 4691377 (1987-09-01), Yoshihara et al.
patent: 4862270 (1989-08-01), Nishio
patent: 4929849 (1990-05-01), Paul

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