Clock recovery apparatus

Details Clock recovery apparatus Clock recovery apparatus

2003-01-28

2004-06-08

Hudspeth, David (Department: 2651)

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

C360S026000

Reexamination Certificate

active

06747826

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock recovery apparatus for recovering a clock signal used to reproduce digital data from an incoming signal.
2. Description of the Background Art
In a signal reproduction apparatus for reproducing digital data from an incoming signal, a clock recovery apparatus for recovering a clock signal synchronized with the reproduced digital data is incorporated therein. In the signal reproduction, the incoming signal is exemplarily sampled with a timing of the recovered clock signal. Hereinafter, a clock signal suitable for reproducing digital data, in other words, an ideal clock signal for the clock recovery apparatus is referred to as data clock, while an actual clock signal is referred to as recovered clock signal.
In the signal reproduction apparatus such as hard disk drive or magnetic tape drive, a signal reproduced from a recording medium is supplied as an incoming signal. In such an apparatus, a PRML (Partial Response Maximum Likelihood) method is applied to record and reproduce digital data. In the signal reproduction apparatus applying the PRML method therein, the reproduction signal is first subjected to partial response equalization and then to most likelihood decoding by going through a Viterbi decoder, for example. In this manner, digital data recorded on the recording medium is reproduced. A description is provided next about a conventional reproduction signal processing part of the signal reproduction apparatus applying the PRML method therein. In
FIGS. 19 and 20
, a thinner arrow-headed signal line indicates an analog signal or a one-bit digital signal, while a thicker arrow-headed signal line indicates a digital signal including two or more bits.
FIG. 19
is a block diagram showing the structure of a reproduction signal processing part into which a first conventional clock recovery apparatus is incorporated. Such structure is found exemplarily in Jenn-Gang Chem, et al. “An EPRML Digital Read/Write Channel IC” 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, SA19.4 (February 1997). In the reproduction signal processing part shown in
FIG. 19
, a reference numeral
101
denotes the clock recovery apparatus. A reproduction signal
10
is a signal reproduced from a recording medium such as magnetic disk or magnetic tape. On the reproduction signal
10
, digital data synchronized with a data clock is presumably recorded. The reproduction signal
10
is amplified in a reproduction amplifier
2
, and the amplified signal is subjected to partial response equalization in an equalizer
3
. An output signal from the equalizer
3
is forwarded to an AD converter
4
, and is sampled and quantized therein with timing of a recovered clock signal
11
to be a decoder input signal
12
. The decoder input signal
12
is subjected to most likelihood decoding in a Viterbi decoder
5
according to Viterbi algorithm, and a result obtained thereby is outputted as reproduction data
13
. The reproduction data
13
is regarded as data reproduced by the signal reproduction apparatus.
The decoder input signal
12
is forwarded also to a phase error detector
6
. Being provided with the decoder input signal
12
, the phase error detector
6
outputs a phase error signal
14
to a DA converter
7
. The phase error signal
14
indicates a difference in phase (hereinafter, phase error) between the data clock and the recovered clock signal
11
. The phase error signal
14
is converted to an analog signal by the DA converter
7
. The analog signal is then forwarded to a loop filter
8
to be an oscillation control signal
15
. The oscillation control signal
15
is forwarded to a VCO (Voltage Controlled Oscillator)
9
. The VCO
9
oscillates according to a frequency controlled by the oscillation control signal
15
, and generates the recovered clock signal
11
. The recovered clock signal
11
is used as a sampling clock in the AD converter
4
. In the first conventional clock recovery apparatus
101
, the recovered clock signal
11
phase-locked to the data clock is generated by a PLL (Phase Locked Loop) circuit by a feed-back loop including the AD converter
4
, the phase error detector
6
, the DA converter
7
, the loop filter
8
, and the VCO
9
.
In the first conventional clock recovery apparatus
101
, the equalizer
3
where partial response equalization is performed on the reproduction signal is an analog circuit. For equalization processing with high accuracy and no adjustment, or in an LSI chip, a digital equalizer is preferable.
FIG. 20
is a block diagram showing the structure of a reproduction signal processing part into which a second conventional clock recovery apparatus is incorporated. In the reproduction signal processing part shown in
FIG. 20
, a reference numeral
102
denotes the clock recovery apparatus. Herein, unlike the first conventional clock recovery apparatus
101
where the analog equalizer
3
performs, partial response equalization before AD conversion, a digital equalizer
16
performs partial response equalization after AD conversion. In the second conventional clock recovery apparatus
102
, the recovered-clock signal
11
phase-locked to the data clock is generated by a PLL circuit structured by a feed-back loop including the AD converter
4
, the equalizer
16
, the phase error detector
6
, the DA converter
7
, the loop filter
8
, and the VCO
9
.
It is preferable, for the PLL circuit in such a clock recovery apparatus, that a range of the maximum difference in frequency between the data clock and the recovered clock signal
11
(hereinafter, pull-in range) is wider. With a wide pull-in range, these two clocks come to be locked even if not being locked at first. The problem herein is, although being structurally more preferable than the first clock recovery apparatus
101
, the clock recovery apparatus
102
has a considerably narrower pull-in range. The reason is as follows: since the equalizer
16
is a digital circuit, the equalizer
16
internally delays the signal
17
on a clock period basis, and accordingly comprehensive delay in the feed-back loop in the PLL circuit is increased. Consequently, the recovered clock signal
11
is delayed being controlled by a phase error between the data clock and the recovered clock signal
11
. Such problem becomes evident in the magnetic tape drive where frequency variation of the reproduction signal is wide. Consequently, such a magnetic tape drive cannot employ the second structure in
FIG. 20
, and thus the equalization processing therein cannot be highly accurate or adjustment-free, or carried out in an LSI chip.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a clock recovery apparatus whose pull-in range remains wider even if a delay in a feed-back loop in a PLL circuit is lengthened. Further, another object of the present invention is to provide a clock recovery apparatus, with a wider pull-in range, being capable of performing partial response equalization in digital processing, and equalization processing with high accuracy, no adjustment, and in an LSI chip.
The present invention has the following features to attain the objects above.
A first aspect of the present invention is directed to a clock recovery apparatus for recovering a clock signal used to reproduce digital data from an incoming signal, the device comprising: an oscillation part for receiving a control signal, and generating, as an oscillation clock signal, a clock signal whose frequency is based on the control signal; a sampling part for sampling the incoming signal with timing of the oscillation clock signal, and outputting a sampled value of the incoming signal; a phase error detection part for detecting, based on the sampled value, a phase error between the oscillation clock signal and an ideal clock signal used to reproduce the digital data; a quality judgement part for judging quality of the sampled incoming signal by referring to the sampled value; a phase-frequency error d

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