Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Comparing counts
Reexamination Certificate
2000-12-26
2003-04-15
Lam, Tuan T. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Comparing counts
C340S146200
Reexamination Certificate
active
06549604
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to the field of signal processing. More particularly, the invention relates to clock recovery and detection of rapid phase transients.
2. Discussion of the Related Art
Clock recovery is a fundamental procedure in all digital receivers. For instance, in T
1
transmission schemes the serial data is transported as a series of (bipolar) pulses wherein the presence of a pulse indicates a digital “1” and absence of a pulse indicates a digital “0.” It is essential that the receiver have an accurate estimate of the duration, separation and position of the pulse (or absence) to decide the nature of the transmitted bit. This, in essence, is the notion of a clock recovery. As one consequence, the receiver makes available a signal that has the same timebase (notion of time interval) as the transmitter.
In synchronization equipment, such as the Symmetricom DCD Series, clock recovery is used to establish a reference timebase. An oscillator locked to this reference is said to be traceable to the transmitter. For specificity, the reference input is assumed to be a DS
1
(or T
1
) signal. This signal is characterized by a (nominal) bit rate of 1.544 Mbps, that is, an underlying clock frequency of (nominally) 1.544 MHz.
Recovering the clock from an incoming T
1
signal involves some reprocessing circuitry which provides an intermediate signal from which the clock is recovered. In particular, analog circuitry provides the functions of AGC (automatic gain control) and “slicing”. Slicing involves setting a threshold for deciding whether the signal voltage is close to zero, which translates to a “digital/0”, or large, corresponding to a “digital 1”. That is, the preprocessing circuitry generates a digital signal (i.e. two level) with a pulse for each instantiation of a pulse in the incoming T
1
signal. Subsequent digital circuitry then uses this signal to generate a (roughly) square wave which is representative of the recovered clock signal.
One technique for deriving the recovered clock signal is described below. This method is used in several Symmetricom products.
Referring to
FIG. 1
, a preprocessed T
1
signal, namely the pulse train obtained using analog circuitry, is called “T
1
-SIG”. A stable clock signal of (nominally) 30 MHz is provided to run the circuitry shown (the dividers shown are appropriate for a 30 MHz digital reference clock; for other choices of reference clock frequency the dividers would have to be modified appropriately). The circuit includes a 13/14 counter (MOD 13/14 CTR). That is, a counter that operates as either a modulo-13 counter or a modulo-14 counter according to the control signal shown (SEL 13+/14−). The signal labeled “TC-H” is high for one clock period every 13 (or 14, depending on which modulo mode is selected) clock periods. The circuit also includes a modulo-18 counter (MOD 18 CTR) with a “clock-enable” control.
The modulo-18 counter operates normally when the control signal “EN-L” is LOW but does not count when “EN-L” is HIGH. The modulo-18 counter (implemented as a binary counter) requires 5 bits of which Q
4
is the most significant. The waveform associated with Q
4
will be nominally square (50% duty cycle) and the mechanism shown forces Q
4
to have a frequency nominally equal to the underlying clock frequency of the T
1
signal.
The combination of the two counters ensures that the frequency of the Q
4
waveform is, very roughly, 1.544 MHz. When the mod-13/14 counter is selected to run in the modulo-13 mode, every 13 clock cycles the modulo-18 counter “skips” one count. Consequently, the frequency associated with the signal Q
4
is (30/18)·(12/13) MHz, which is 1.538461 . . . MHz. When the modulo-14 mode is selected, the frequency associated with Q
4
is (30/18)·(13/14) MHz which is 1.547619 . . . MHz. By switching back and forth between these two modes, the average frequency of Q
4
can be made equal to the underlying frequency of the incoming T
1
signal.
This action is depicted in FIG.
1
. If the rising edge of a pulse in T
1
-SIG occurs prior to the rising edge of Q
4
, then the flip-flop (“FF”) output will be LOW which causes the counter scheme to go into the modulo-14 mode, effectively using the higher frequency which, in turn, tends to make the rising edges of Q
4
to occur earlier. If the rising edge of T
1
-SIG occurs after the rising edge of Q
4
, the modulo-13 or lower frequency mode will be selected causing the rising edge of Q
4
to be aligned to the instants where T
1
-SIG has rising edges. The associated timing diagram is depicted in FIG.
2
.
The output of FF (flip-flop) indicates whether recovered clock is faster or slower than the implied T
1
clock. The FF output is “held” when T
1
-SIG has “missing” pulse. The time-average of the FF output is a measure of frequency difference between T
1
and 30 MHz reference.
FIG. 2
is not drawn to scale. However,
FIG. 2
illustrates the key points of the clock recovery scheme. The top trace denotes T
1
-SIG. Note that when the T
1
signal has a data bit of “0”, the corresponding occurrence in T
1
-SIG is a “missing pulse”. The second trace indicates the waveform of Q
4
and the bottom trace the waveform associated with the control signal that chooses the modulo-13/modulo-14 operation. The time average (measured over a significant number of clock cycles) of the FF output is indicative of the frequency of the T
1
signal relative to the local reference (30 MHz, nominal, in the above example). In particular, let p
13
be the fraction of time that the signal FF is HIGH. Then p
14
=(1−p
13
) is the fraction of time the signal FF is LOW. Clearly, p
13
is the fraction of time that the modulo-13 divider is operative and p
14
is the fraction of time the modulo-14 counter is active. The overall action of the circuit is to “lock” the frequency of Q
4
to the underlying T
1
frequency. Thus the following equation can be postulated:
F
T1
≅
f
Q4
≅
f
R
·
[
ρ
13
·
12
13
·
1
18
+
ρ
14
·
13
14
·
1
18
]
Where f
T1
, f
Q4
and f
R
are the frequencies of the T
1
signal, the recovered clock signal, and the local reference clock signal, respectively.
When the T
1
signal has a data bit of “0”, there is a missing pulse in T
1
-SIG. The action of the circuit is to “hold” the previous control value for the mod-13/mod-14 counter. Thus if there is a long string of “0”s in the T
1
signal then there will be significant periods of time where the frequency of Q
4
is high (1.547619 . . . MHz) or low (1.538461 . . . MHz). The absence of any pulse in T
1
-SIG during this period implies that the circuit cannot correct for this apparent malfunction. However, in the applications of Symmetricom Synchronization products, the T
1
signal is supposed to be a “framed-all-1s” signal and the preponderance of data bits are “1.” Data bits of “0” occur only via the framing pattern and thus the worst-case scenario is one “0” in 193 bits.
SUMMARY OF THE INVENTION
There is a need for the following embodiments. Of course, the invention is not limited to these embodiments.
One embodiment of the invention is based on a method, comprising: incrementing a high counter once every clock cycle if a state variable indicator is high; clearing a low counter if the state variable indicator is high; incrementing the low counter once every clock cycle if the state variable indicator is low; clearing the high counter if the state variable indicator is low; and triggering an alarm signal if either i) the low counter exceeds a low count threshold or ii) the high counter exceeds a high count threshold. Another embodiment of the invention is based on an apparatus, comprising: a source of a clock signal; a source of a state variable indicator coupled to the source of the clock signal; a high counter coupled to the source of the clock signal and the source of a state variable indicator, the high counter incremented once every clock cycle if the state variable ind
Gray Cary Ware & Freidenrich LLP
Lam Tuan T.
Symmetricom, Inc.
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