Clock recovering circuit utilizing a delay locked loop for...

Details Clock recovering circuit utilizing a delay locked loop for... Clock recovering circuit utilizing a delay locked loop for...

2006-09-05

2006-09-05

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C327S163000, C375S376000

Reexamination Certificate

active

07102403

ABSTRACT:
A clock recovering circuit for generating an output clock locked to an analog input signal includes: a phase detection unit for receiving the analog input signal and the output clock for generating a phase error signal according to the analog input signal and the output clock; a loop filter coupled to the phase detector for filtering the phase error signal and generating a control signal; a numerically controlled oscillator (NCO) coupled to the loop filter for generating a first clock and an index signal according to the control signal; a delay locked loop (DLL) coupled to the NCO for receiving the first clock and generating a plurality of second clocks; and a multiplexer coupled to the NCO and the DLL for selecting one of the second clocks as the output clock according to the index signal.

REFERENCES:
patent: 5977805 (1999-11-01), Vergnes et al.
patent: 6424185 (2002-07-01), Wolf
patent: 6983032 (2006-01-01), Mujica et al.

Affiliated with

Also associated with

Rating

Clock recovering circuit utilizing a delay locked loop for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock recovering circuit utilizing a delay locked loop for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock recovering circuit utilizing a delay locked loop for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3531165