Clock receiver circuit for on-die salphasic clocking

Details Clock receiver circuit for on-die salphasic clocking Clock receiver circuit for on-die salphasic clocking

2001-08-29

2003-09-02

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S164000

Reexamination Certificate

active

06614279

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to microelectronic circuits and, more particularly, to clock receiver circuits for use therein.
BACKGROUND OF THE INVENTION
The operational speed of microprocessors and other microelectronic circuits (e.g., digital integrated circuits) is continuously increasing. As clock frequencies increase, proportionately lower clock skews are generally required. As such, clock distribution has become a major on-chip performance bottleneck within such circuits. One clock distribution strategy that has been successfully implemented in board level circuit designs (i.e., non-microelectronic circuits) to provide reduced clock skew is known as salphasic clocking. Salphasic clocking makes use of standing waves to distribute a clock signal within an electrical system. For various reasons, salphasic clocking has been difficult to implement on-die within microelectronic circuits. Therefore, practical methods and structures for implementing salphasic clocking within microelectronic circuits are generally desired.


REFERENCES:
patent: 5446396 (1995-08-01), Brehmer
patent: 5465058 (1995-11-01), Krenik et al.
patent: 6236270 (2001-05-01), Takeuchi
patent: 6294940 (2001-09-01), Kiehl

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