Clock re-timing apparatus with cascaded delay stages

Details Clock re-timing apparatus with cascaded delay stages Clock re-timing apparatus with cascaded delay stages

1995-10-25

1997-09-02

Lee, Michael H.

Television

Synchronization

Automatic phase or frequency control

327161, 327237, 327269, H03L 700

Patent

active

056637675

ABSTRACT:
A video clock input signal is applied to a delay line comprising a cascade connection of a plurality of delay elements formed in an integrated circuit for providing a plurality of delayed clock signals at respective taps of the delay line. A selection circuit, responsive to a horizontal synchronizing signal supplied thereto, couples a selected one of the taps to an output for providing a delayed output clock signal that is edge-aligned with the synchronizing signal. For reducing the number of taps required to provide a given minimum delay step resolution and a given minimum total delay for delay elements which may vary in delay, from one integrated circuit to another, the taps are spaced one element apart for a first group of the delay elements and are spaced more than one element apart for at least one second group of the elements.

REFERENCES:
patent: 4638360 (1987-01-01), Christopher et al.
patent: 4667240 (1987-05-01), Willis et al.
patent: 4782391 (1988-11-01), NcNeely et al.
patent: 4992874 (1991-02-01), Willis et al.
patent: 5031167 (1991-07-01), Ishibashi et al.
patent: 5309111 (1994-05-01), NcNeely et al.
patent: 5365128 (1994-11-01), Bazes
patent: 5374860 (1994-12-01), Llewellyn
patent: 5487095 (1996-01-01), Jordan et al.

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