Clock ratio data synchronizer

Details Clock ratio data synchronizer Clock ratio data synchronizer

2006-01-03

2006-01-03

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S144000, C327S145000, C375S355000

Reexamination Certificate

active

06982575

ABSTRACT:
A clock ratio data synchronizer is provided that utilizes a plurality of flip flops to synchronize data received by the synchronizer from first clock domain logic at a first clock frequency to a clock frequency of second clock domain logic. Each flip flop is capable of sampling data only on an edge of a clock and outputting data only on an edge of the clock. By utilizing flip flops in the synchronizer, data values are only allowed to change on clock edges. This, in turn, greatly improves clock skew tolerance, and also setup time margins for the first clock domain logic and for the second clock domain logic.

REFERENCES:
patent: 4949361 (1990-08-01), Jackson
patent: 5528237 (1996-06-01), Moloney et al.
patent: 5896052 (1999-04-01), Gujral et al.
patent: 5999023 (1999-12-01), Kim
patent: 6359479 (2002-03-01), Oprescu

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