Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
1999-10-26
2001-04-10
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S293000, C327S259000
Reexamination Certificate
active
06215346
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock pulse generator. Such a generator may be used in high speed low power controller circuits, for instance in complex very large scale integrated (VLSI) designs including digital signal processing (DSP). The clock pulse generator may advantageously be used in addressing for driver circuits of spatial light modulators and displays, for example of the pixelated matrix type in which a sequence of well-defined pulses must be supplied to circuits which sample high speed video data.
2. Description of the Related Art
A known type of clock pulse generator is based on a shift register. The shift register comprises a cascaded chain of D-type flip-flops which respond to clock pulses to pass a single stored logic state from one flip-flop to the next in the chain. For a typical clock pulse generation application, all but one of the states of the flip-flops are initialised to a logic low (0) state whereas the remaining flip-flop is initialised to a logic high (1) state. The shift register is clocked at a known frequency and the circulating one state within the shift register is used to generate sequential pulses at the outputs of the flip-flops. This well-known technique is disclosed, for example, in U.S. Pat. No. 4,542,301 and U.S. Pat. No. 4,612,659. An improvement to this technique is disclosed in U.S. Pat. No. 4,785,297. In this case, the “master” and “slave” outputs of each of the flip-flops are used in conjunction with combinational logic gates, such as AND or NAND gates, to reduce the clocking speed of the shift register for a given number of output pulses.
It is also well-known to form clock pulse generating circuits from chained D-type latch circuits.
FIG. 1
of the accompanying drawings illustrates part of a typical CMOS circuit comprising latches
1
and
2
. The construction and operation of such an arrangement is well-known and will not be described in detail. Consecutive latches such as
1
and
2
are transparent on opposite clock phases of a two phase clock represented by CK and CK−. The input and output of each latch are “NANDed” together in order to produce the clock pulses Nn and Np as illustrated in
FIG. 2
of the accompanying drawings.
FIG. 2
also illustrates the two phase clock waveforms, the D input to the first latch
1
, the output M of the first latch
1
which is also the input of the second latch
2
, and the output Q of the second latch
2
.
This arrangement has several disadvantages. In particular, a two phase clock is required to drive the shift register. Also, each clock line drives two transistor gates in each of the latches
1
,
2
. This presents a relatively high capacitive loading to each clock phase and limits the maximum frequency of operation. Further, the output pulses Nn and Np cannot be guaranteed to be non-overlapping. This can cause problems in certain applications, for example when the output pulses are used for sampling video data in pixel matrix display drivers.
Various techniques have been disclosed for reducing the capacitive loading of the clock line or lines so as to increase the maximum frequency of operation and reduce clock power consumption. For example, state-controlled clocking techniques have been suggested for use in clock pulse generating circuits. An example of this is disclosed in U.S. Pat. No. 4,746,915, in which the shift register is divided into several sub-registers of flip-flops or latches and another shift register operating at a lower frequency is used selectively to apply the clock signal to each sub-register.
For applications in which the requirement is for a single circulating 1 state, only those flip-flops or latches containing a 1 state or having a 1 state at their input require clocking. As shown in
FIG. 3
, for such applications, the signal generated by “ORing” the input and output of each flip-flop can be used to gate the clock signals supplied to the clock input of the flip-flop. Such an arrangement is disclosed in T. Maekawa et al, “A 1.35-in.-diagonal wide-aspect-ratio poly-Si TFT LCD with 513 k pixels” Journal of the Society or Information Display, pp 415-417, 1994. However, such an arrangement requires a full flip-flop and several further transistors per stage. Also, the flip-flop outputs have to drive a relatively large load and this limits the maximum speed of operation.
SUMMARY OF THE INVENTION
The term “pass gate” as used herein is defined to mean a semiconductor arrangement having a main conduction path which can be controlled to transmit or block the passage of an input signal.
According to a first aspect of the invention, there is provided a clock pulse generator comprising a clock input and N stages where N is greater than three, each ith one of the stages comprising a pass gate arranged to be controlled by a control signal from the (i−1)th stage for passing a clock pulse from the clock input to an output of the pass gate and a control signal generating circuit responsive to the output of the pass gate for supplying a control signal to the (i+1)th stage, the control signal generating circuit being arranged to be inhibited from supplying further control signals in response to a control signal from the (i+2)th stage, where 1<i<(N−1).
The control signal generating circuit of each ith stage may comprise first and second metal-oxide-silicon field effect transistors of opposite conductivity types connected in series between first and second power supply inputs, the gate of the first transistor being connected to the output of the pass gate and the gate of the second transistor being connected to the control signal generating circuit of the (1+2)th stage.
Each ith stage may comprise a switching arrangement for selectively causing the pass gate to be controlled by control signal from the (i+1)th stage and the control signal generating circuit to be inhibited in response to a control signal from the (i−2)th stage. The switching arrangement may comprise a plurality of further pass gates connected to the output of the control signal generating circuit and having control inputs for receiving direction control signals.
At least one of the pass gate outputs may constitute outputs of the generator.
At least one of the control signals or the complements thereof may constitute output signals of the generator.
The pass gates may have inputs connected to the clock input.
Each ith stage may comprise an inverter having an input connected to receive the control signal for the pass gate and an output connected to the pass gate.
Each of the pass gates may be a transmission gate comprising third and fourth metal-oxide-silicon field effect transistors of opposite conductivity types whose source-drain paths are connected in antiparallel. The gate of the fourth transistor may be connected to the output of the inverter and the gate of the third transistor may be connected to the input of the inverter.
The pass gate of each ith stage may comprise a fifth metal-oxide-silicon field effect transistor of the same conductivity type as the first transistor.
The clock input may be a single phase clock input. The clock pulses passed by the pass gates of consecutive stages may be of opposite polarity. The third transistors of the transmission gates of consecutive stages may be of opposite conductivity types. The first transistors of consecutive stages may be of opposite conductivity types.
The clock input may be a two-phase clock input. The pass gate inputs of consecutive stages may be connected to different clock input phases. The clock pulses passed by the pass gates of the stages may be of the same polarity. The third transistors of the stages may be of the same conductivity type. The first transistors of the stages may be of the same conductivity type.
The pass gate output of each sage may be provided with a pull-up or pull-down transistor. Each of the pull-up or pull-down transistors may have a control electrode connected to the input or output of the inverter.
Each of the stages may have a
Brownlow Michael J.
Cairns Graham A.
Callahan Timothy P.
Nguyen Hai L.
Renner , Otto, Boisselle & Sklar, LLP
Sharp Kabushiki Kaisha
LandOfFree
Clock pulse generator, spatial light modulator and display does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Clock pulse generator, spatial light modulator and display, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock pulse generator, spatial light modulator and display will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2554765