Clock pulse generator

Details Clock pulse generator Clock pulse generator

1997-05-15

1999-08-10

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327154, 327362, H03L 700

Patent

active

059364416

ABSTRACT:
A simply structured clock pulse generator operating stably in a wide range of frequencies in response to a timing signal fed from outside a semiconductor integrated circuit. A first frequency signal fed from the external terminal of the semiconductor integrated circuit and a second frequency signal generated within the semiconductor integrated circuit are input to a phase comparator. The output signal of the phase comparator is smoothed by a low-pass filter for conversion to a voltage signal. A compensation circuit uses both a delay signal from a current-controlled delay circuit receiving the first frequency signal and the first frequency signal to generate a current signal corresponding to the frequency of the latter signal. The voltage signal generated by the low-pass filter is converted into a current signal. This current signal is combined with the current signal from the compensation circuit to control the oscillation frequency of a ring oscillator comprising a current-controlled delay circuit the same in structure as the above current-controlled delay circuit. On the basis of the oscillation signal from the ring oscillator, the second frequency signal and clock signals needed in the semiconductor integrated circuit are generated.

REFERENCES:
patent: 5638014 (1997-06-01), Kurita
M. Johnson et al., "A Variable Delay Line PLL for CPU-Coprocessor Synchronization", IEEE Journal of Solid-State Circuit, vol. 23, No. 5, Oct. 1988, pp. 1218-1223.
D. Jeong et al., "Design of PLL-Based Clock Generation Circuits", IEEE Journal of Solid-State Circuit, vol. SC-22, No. 2, Apr. 1987, pp. 255-261.

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