Clock processing logic and method for determining clock...

Details Clock processing logic and method for determining clock... Clock processing logic and method for determining clock...

2005-03-15

2005-03-15

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S291000

Reexamination Certificate

active

06867630

ABSTRACT:
Clock processing logic and method for determining clock signal characteristics in reference voltage and temperature varying environments are described. A sample vector is characterized by bit locations corresponding to sequentially increasing delay values so that values stored in such bit locations indicate clock signal edges where value transitions occur. In one embodiment, edge detection logic and sensitivity adjustment logic are used in determining the clock period from such a sample vector. In another embodiment, an edge filter, sample accumulation logic, and clock period and jitter processing logic are used in determining an average clock period and clock jitter from a predefined number of such sample vectors.

REFERENCES:
patent: 6031401 (2000-02-01), Dasgupta
patent: 6548997 (2003-04-01), Bronfer et al.
patent: 6721255 (2004-04-01), Gushima et al.
Ryan, Kevin, “DDR SDRAM Functionally and Controller Read Data Capture,” DesignLine, Micron Technology, Inc., vol. 8, Issue 3, 3Q99.

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