Clock phasing circuit

Details Clock phasing circuit Clock phasing circuit

1975-06-17

1976-09-14

Robinson, Thomas A.

Telegraphy

Systems

Line-clearing and circuit maintenance

179 15BS, 325321, 328 63, 328155, H04L 700

Patent

active

039808203

ABSTRACT:
A clock phasing circuit for aligning data which is transmitted by a first clock, running at a particular frequency, with a second clock running at the same frequency as the first clock but in a different and undetermined phase relationship. The incoming data includes a synchronizing signal which initiates the operation of the clock phasing circuitry so that the data is alternately clocked into each of a pair of flip flops by successive pulses from the first clock. Each flip flop is individually connected to one of the inputs of one logic gate of a pair of gates which are alternately enabled by successive pulses from the second clock. The outputs from the two logic gates are combined by a further logic gate so that the data is reformed in alignment with the second clock.

REFERENCES:
patent: 3188569 (1965-06-01), Mahony
patent: 3593160 (1971-07-01), Moore
patent: 3725590 (1973-04-01), Verstegen
patent: 3808368 (1974-04-01), Pitroda et al.
patent: 3825683 (1974-07-01), Pitroda et al.
patent: 3829843 (1974-08-01), Cichetti, Jr. et al.
patent: 3839599 (1974-10-01), Pitroda
patent: 3894246 (1975-07-01), Torgrim

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