Clock phase synchronizing circuit

Details Clock phase synchronizing circuit Clock phase synchronizing circuit

1997-03-31

1999-01-05

Grant, Chris

Television

Synchronization

Automatic phase or frequency control

348536, H04N 512

Patent

active

058568514

ABSTRACT:
When the margin between a write frequency-divided clock signal and a read frequency-divided clock signal becomes remarkably decreased, a clock phase difference detecting circuit outputs a reset execution command. While a reset execution command is being output in a blanking interval, a reset signal generating circuit supplies a reset signal to an input side counter corresponding to a reset execution command so as to reset the phase of the write frequency-divided clock signal to an initial state.

REFERENCES:
patent: 4165524 (1979-08-01), Ninomiya
patent: 4249198 (1981-02-01), Ito et al.
patent: 4673980 (1987-06-01), Murakami et al.
patent: 4688081 (1987-08-01), Furuhata et al.
patent: 5453885 (1995-09-01), Takeshita et al.
patent: 5528307 (1996-06-01), Owada et al.
Y. Otsuka, et al., "A Study of Bit Synchronization Circuit For High-Speed Switching Systems", SSE89-114, pp. 37-42.

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