Clock phase correction circuit

Details Clock phase correction circuit Clock phase correction circuit

1999-05-28

2000-10-24

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327161, H03L 706

Patent

active

061373281

ABSTRACT:
A clock phase correction circuit for a semiconductor memory device reduces all lock ranges by using a half-mixer to a conventional delay locked loop (DLL) circuit, and thus generates a clock signal having a fast lock time and a very small jitter. In order to achieve this objective, a track portion having a plurality of phase converters and one half-mixer is provided between an input terminal of external clock and an input terminal of a delay means of the conventional DLL circuit, and approaches the phase of the external clock to a phase of the feedback clock. A phase difference between the corrected signal and the feedback clock is then reduced by the conventional DLL circuit. As a result, lock time becomes shorter, and the magnitude of a jitter becomes reduced.

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