Clock phase adjustment method, and integrated circuit and...

Details Clock phase adjustment method, and integrated circuit and... Clock phase adjustment method, and integrated circuit and...

2001-07-12

2003-04-29

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06556505

ABSTRACT:

TECHNOLOGICAL FIELD
The present invention relates to a clock phase adjustment method, and an integrated circuit and a method for designing the integrated circuit.
BACKGROUND ART
When writing data into a synchronous DRAM (Synchronous Dynamic Random Access Memory, hereinafter referred to as a SDRAM) or reading data from the SDRAM (hereinafter referred to as data access), it is difficult to make appropriate timing because of a high-speed operating clock. Therefore, conventionally, a LSI that makes data access to the SDRAM is fabricated initially, and then the phase of the clock is adjusted by trial and error.
Further, Japanese Published Patent Application No. Hei.9-185427 discloses a clock phase adjustment circuit and a clock phase adjustment method for making timing of access to a SDRAM.
FIG. 13
is a circuit diagram illustrating a memory interface circuit to which a clock phase adjustment circuit as disclosed in Japanese Published Patent Application No. Hei.9-185427 is applied. A memory interface device
700
comprises a clock frequency converter
710
, two input buffers
711
and
720
, a clock phase adjustment circuit
712
, three output buffers
715
,
717
, and
719
, and three flip-flops (FF)
716
,
718
, and
721
. The interface device
700
outputs an external clock signal, a SDRAM command, and data to a SDRAM
702
.
The clock phase adjustment circuit
712
is a circuit for adjusting the phase of a clock signal to execute appropriate data access to the SDRAM
702
, and it inverts the phase of a clock signal as a reference of operation by 180 degrees, and outputs the clock signal to the SDRAM
702
. The clock phase adjustment circuit
712
is composed of an inverter
713
, a phase converter
714
, and a selector
744
.
The phase converter
714
is provided with clocks having different delay values. After the memory interface device
700
is connected to the SDRAM
702
, operable clocks are tested by appropriate means, and a clock, which is judged as being appropriate on the basis of the result of the text, is selected.
The conventional clock phase adjustment is carried out by trial and error after fabricating an actual LSI. That is, since the design engineer adjusts the clock phase by repeating trial and error after the LSI is fabricated, the process steps relating to the fabrication of the LSI are complicated.
Further, in the interface device
700
as disclosed in Japanese Published Patent Application No. Hei.9-185427, a lot of delay elements relating to clock phase adjustment are required, whereby the circuit scale is increased, and the power consumption is also increased.
Further, since the data inputted to the interface device
700
passes through various circuits and buffers before it is outputted from the device
700
, when the interface device
700
is implemented in a practical LSI, the delays of clocks might be greatly different from those expected, resulting in difficulty in determining the delay values of the delay elements. In this case, although determination of the delay values may be facilitated by preparing more delay clocks, this causes a new problem that the circuit scale and the power consumption are further increased.
Furthermore, since the delay values cannot be known unless the interface device
700
is actually connected to the SDRAM
702
, it is necessary to perform, after connecting the interface circuit
700
to the SDRAM
702
, a test of data transfer to select a clock of optimum delay value, whereby the number of process steps relating to the circuit fabrication increases.
Moreover, since external factors (wiring delay, external load, etc.) are not considered in the interface device
700
, the precision is degraded. Further, in order to consider the external factors, a test of data transfer must be performed for every substrate to select a clock, whereby the number of process steps relating to the circuit fabrication increases.
The present invention provides a clock phase adjustment method that realizes clock phase adjustment in the designing stage, with reduced number of process steps relating to fabrication of a device that makes access to an external memory, without performing phase adjustment by trial and error, and without performing a test for clock phase adjustment. This clock phase adjustment method realizes supply of more reliable clocks, with minimum required circuits, even in perfect synchronous design, and realizes automatic clock phase adjustment even when a feedback clock system is employed.
Further, the present invention provides an integrated circuit and a design method thereof, which realize data access on the basis of a high-speed operating clock, without requiring complicated structure like the conventional circuit.
DISCLOSURE OF THE INVENTION
In order to achieve the above-mentioned objects, an integrated circuit according to the present invention has the following construction. That is, an integrated circuit, which makes data access to an external memory in synchronization with a clock, comprises: a clock generator for generating the clock; at least one first clock buffer for driving the clock as an external clock; at least one second clock buffer for driving the clock as an internal clock; a clock output buffer for outputting the external clock to the external memory; a data output flip-flop for outputting data to he outputted to the external memory, in synchronization with the internal clock; and an input flip-flop for capturing data outputted from the external memory, in synchronization with the internal clock; wherein a value of a phase difference D obtained by subtracting “the time from when the external clock is outputted from the clock generator to when it reaches the clock output buffer” from “the time from when the internal clock is outputted from the clock generator to when it reaches the data output flip-flop” is set so as to satisfy first to fourth conditions as follows: first condition: a first value obtained by subtracting “the time from when the external clock is outputted from the clock generator to when it reaches the external memory” from the sum of “the time from when the internal clock is outputted from the clock generator to when it reaches the data output flip-flop” and “the time from when data is outputted from the data output flip-flop by the internal clock that has reached there to when the data reaches the external memory” should be larger than the data hold time of the external memory; second condition: a value obtained by subtracting the first value from “the time corresponding to one cycle of the external clock” should be larger than the data setup time of the external memory; third condition: a value obtained by subtracting “the time from when the internal clock is outputted from the clock generator to when it reaches the input flip-flop” from the sum of “the time from when the external clock is outputted from the clock generator to when it reaches the external memory” and “the hold time of data to be outputted from the external memory on receipt of the external clock” and “the time from when the data is outputted to when it reaches the input flip-flop” should be larger than the data hold time of the input flip-flop; and fourth condition: a value obtained by subtracting the sum of “the time from when the external clock is outputted from the clock generator Lo when it reaches the external memory” and “the output delay time of data to be outputted from the external memory on receipt of the external clock” and “the time from when the data is outputted to when it reaches the input flip-flop” from the sum of “the time corresponding to one cycle of the internal clock” and “the time from when the internal clock is outputted from the clock generator to when it reaches the input flip-flop” should be larger than the data setup time of the input flip-flop.
Accordingly, the present invention can provide an integrated circuit that performs appropriate data transfer and clock supply, without having a complicated circuit like the conventional circuit in which plural delay elements are inserted in plural sign

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