Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1988-10-07
1989-08-22
Miller, Stanley D.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
328 55, 328 56, 307602, 307603, 307605, 307606, 307511, 307262, H03K 513, H03K 5159, H03K 500, H03L 700
Patent
active
048599549
ABSTRACT:
A clock phase adjusting system is provided, including: a scan in/our apparatus, having (n+1) special scan-out latch circuits; a first delay device which selectively outputs an input clock as a delay clock output of a maximum m=2.sup.n steps in accordance with an (n) bit selection signal; a second delay device which selectively outputs the input clock signal as the delay clock signals of further minimum 1/2.sup.P steps of a minimum step width by the first delay device in accordance with the (P) bit selection signal and which is connected in cascade with the first delay device, so that the delayed clock signals of 1/2.sup.P steps are output as the input clock signal by only setting, in the (n+p) scan in/out latch circuits, the selection data for obtaining a delay clock signal.
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patent: 4580066 (1986-04-01), Berndt
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patent: 4700347 (1987-10-01), Rettberg et al.
DasGupta, "LSSD Scan Technique", vol. 24, No. 8, Jan. 1982, IBM Tech. Disclosure Bulletin.
Hahn et al, "VLSI Testing by On--Clip Error Detection", IBM Tech Disclosure Bulletin, vol. 25, No. 2, Jul. 1982.
Fujitsu Limited
Miller Stanley D.
Phan Trong Quang
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