Clock period sensing circuit

Details Clock period sensing circuit Clock period sensing circuit

2001-03-19

2002-05-14

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S276000, C327S277000

Reexamination Certificate

active

06388490

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a clock period sensing circuit and, more particularly, to a clock delay sensing circuit capable of sensing delay and finely adjusting the same.
BACKGROUND OF THE INVENTION
Examples of conventional clock delay sensing circuits include a series of sensing circuits comprising a series of inverters, and means for sensing delay from the number of stages of a ring oscillator. For example, as shown in
FIG. 10
, there is known an arrangement in which a period sensing circuit
206
comprises a ring oscillator of a fixed number of stages and a counter, in which the oscillation frequency of the ring oscillator in the period of an input clock is counted by the counter to sense the clock period.
Further,
FIG. 11
illustrates an example of the construction of a synchronous delay circuit according to the prior art. This circuit has as its basic components a first delay circuit line
901
for measuring delay (“measuring delay line”) and a second delay circuit line
902
for reconstructing delay (“synchronizing delay line”), the direction of signal propagation of the latter being the opposite of the former. The output end of the second delay circuit line
902
is connected to an output buffer (having a delay time td
2
), and a transfer control circuit
903
is provided between the first delay circuit line
901
and second delay circuit line
902
. The transfer control circuit
903
turns on upon receiving an output from an input buffer
904
. A dummy delay circuit
906
having a delay time td
1
+td
2
is inserted between an output end of the input buffer
904
and an input end of the first delay circuit line
901
.
An input clock signal enters the first delay circuit line
901
from the input buffer
904
and propagates through the first delay circuit line
901
by the time the next pulse enters following the clock signal period (tCK). At the moment the next pulse enters, the transfer control circuit
903
turns on so that a pulse that has propagated through the first delay circuit line
901
over a period of time equal to (tCK−td
1
−td
2
) enters the second delay circuit line
902
from this position, propagates through and is output from the second delay circuit line
902
over the time period (tCK−td
1
−td
2
) of propagation through the first delay circuit line
901
. The pulse is output via an output buffer
905
(whose delay time is td
2
). Thus, a signal delayed by 2tCK from the input In is output at an output terminal Out, where [input buffer (td
1
)]+[delay circuit (td
1
+td
2
)]+{first and second delay circuits [2×(tCK−td
1
−td
2
)]}+[output buffer (td
2
)]=2tCK.
SUMMARY OF THE DISCLOSURE
In this arrangement of the conventional delay sensing circuit comprising a series of inverters in which the inverter is a unit delay circuit, the unit of delay is decided by the propagation delay time of one inverter stage. Consequently, if the clock period in a subsequent stage is to be finely adjusted, it is required that the unit of delay used in coarse adjustment be changed over at the ends of the operating range. The reason for this is that there is no overlapping of operating ranges in terms of the individual units of delay.
Accordingly, it is an object of the present invention to provide a clock period sensing circuit in which it is possible to broaden the operating range of phase adjustment and frequency multiplier circuits, etc. It is another object of the present invention to provide a clock period sensing circuit in which it is possible to broaden the operating range of phase adjustment and frequency multiplier circuits, etc., particularly allowing performing coarse period adjustment in advance.
According to a first aspect of the present invention, the foregoing object is attained by providing a clock period sensing circuit comprising: a plurality of parallel connected delay sensing circuits having slightly overlapping operating ranges and different centers of operation, wherein a clock signal is passed through the plurality of delay sensing circuits, and the period of the clock is sensed using a signal which identifies delay sensing circuits through which the clock signal has passed and delay sensing circuits through which the clock signal has not passed.
According to a second aspect of the present invention, there is provided a clock period sensing circuit comprising: a plurality of delay circuits to which a clock signal is applied as a common input and which are arranged in parallel and have delay times that differ from one another; a plurality of latch circuits to which outputs of respective ones of the delay circuits are input for latching the clock signal as a latch timing signal; and a plurality of encoder circuits to which the outputs of the latch circuits are input for encoding information representing a boundary between delay circuits traversed by the clock signal and delay circuits not traversed by the clock signal, and outputting the encoded information as a control signal.
According to a third aspect of the present invention, the clock period sensing circuit is characterized in that the plurality of delay circuits have operating ranges that overlap each other slightly and centers of operation that differ from one another.
According to a fourth aspect of the present invention, the clock period sensing circuit is characterized in that each of the delay circuits has:
a P-type transistor which is connected between a power supply and an internal node and to which a signal obtained by inverting an input signal is applied as a gate input; and
an N-type transistor, which is driven by a constant-current source, connected between the internal node and ground and to which the signal obtained by inverting the input signal is applied as a gate input;
a plurality of serially connected switches and capacitors being connected in parallel between the internal node and ground, and delay time being decided by deciding a capacitance applied to the internal node by a capacitance control signal connected to a control terminal of each switch;
the delay circuit having an inverter for inverting and outputting a potential present at the internal node.
According to a fifth aspect of the present invention, there is provided a timing dividing circuit (interpolator) comprising:
first, second and third timing dividing circuit (interpolator)s connected in parallel and each having a P-type transistor which is connected between a power supply and an internal node and to which a signal obtained by taking NAND between first and second input signals is applied as a gate input, and first and second N-type transistors, which are driven by a constant-current source, connected between the internal node and ground and to which signals obtained by inverting the first and second input signals are applied as gate inputs; a plurality of serially connected switches and capacitors being connected in parallel between the internal node and ground, and delay time being decided by deciding a capacitance applied to the internal node by a capacitance control signal connected to a control terminal of each switch; each timing dividing circuit (interpolator) having an inverter for inverting and outputting a potential present at the internal node;
wherein a first clock of two clocks having different phases is supplied commonly as the first and second input signals to the first timing dividing circuit (interpolator);
first and second clocks constituting the two clocks having the different phases are supplied as the first and second input signals to the second timing dividing circuit (interpolator); and
a second clock of the two clocks having the different phases is supplied commonly as the first and second input signals to the third timing dividing circuit (interpolator);
the capacitance of the timing dividing circuit (interpolator) being selected by the control signal from the clock period sensing circuit according to any one of the first to fourth aspects.
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