Clock multiplying delay-locked loop for data communications

Details Clock multiplying delay-locked loop for data communications Clock multiplying delay-locked loop for data communications

2005-10-04

2005-10-04

Ho, Duc (Department: 2665)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S503000

Reexamination Certificate

active

06952431

ABSTRACT:
In a communications system, data is multiplexed onto a transmission medium at a transmitter and demultiplexed from the transmission medium at a receiver. The clock applied to the transmitter and receiver is a multiplying delay-locked loop in which a delay line provides a multiplied clock which is applied back to its input. A delay adjustment circuit including a proportional phase comparator of low offset adjusts delay in the delay line.

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