Clock multiplier/jitter attenuator

Details Clock multiplier/jitter attenuator Clock multiplier/jitter attenuator

1987-05-19

1989-02-14

Pellinen, A. D.

Pulse or digital communications

Spread spectrum

Direct sequence

375110, 331 1A, H04L 700

Patent

active

048051985

ABSTRACT:
A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.

REFERENCES:
patent: 4129748 (1978-12-01), Saylor
patent: 4539531 (1985-09-01), Thomas et al.
patent: 4551845 (1985-11-01), ab der Holden et al.
patent: 4633488 (1986-12-01), Show
Yarak, Dennis et al., "A 2.56 Mb/s Digital Local-Loop Transmitter/Receiver," 1985 IEEE International Solid-State Circuits Conference, 32nd ISSCC. Digest of Technical Papers, pp. 154-155, 330, New York, N.Y.

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