Clock multiplier having two feedback loops

Details Clock multiplier having two feedback loops Clock multiplier having two feedback loops

1998-01-14

1999-11-09

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327116, 327159, 327160, 377 47, H03K 2100

Patent

active

059822082

ABSTRACT:
A clock multiplier controls the frequency of an output clock signal according to the frequency of an input clock signal by means of two feedback loops. The first feedback loop, active during a fixed number of initial cycles of the input clock signal, counts cycles of the output clock signal during each cycle of the input clock signal, and controls the output clock frequency according to the resulting count values. The second feedback loop, used after the fixed number of initial cycles, divides the frequency of the output clock signal, and controls the output clock frequency according to the phase difference between the resulting divided signal and the input clock signal.

REFERENCES:
patent: 3769597 (1973-10-01), Mayer
patent: 5317283 (1994-05-01), Korhonen
patent: 5487084 (1996-01-01), Lindholm

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