Clock multiplier circuit capable of generating a high...

Details Clock multiplier circuit capable of generating a high... Clock multiplier circuit capable of generating a high...

1999-02-02

2001-07-24

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S119000, C327S158000, C327S159000

Reexamination Certificate

active

06265916

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to a clock multiplier circuit. More specifically, the invention relates to a clock multiplier circuit suitably used for generating a high frequency clock signal having small jitters from a low frequency input clock signal.
FIG. 1
is a circuit diagram showing a conventional digital phase locked loop (which will be hereinafter referred to PLL) circuit (see the Japanese Official Gazette of Patent Application Laid-Open No. 9-238072). The digital PLL circuit of
FIG. 1
comprises: a 1/M divider
1
for dividing a reference clock signal by M; a frequency comparator circuit
2
for comparing the frequencies of outputs of the 1/M divider
1
and a 1N divider
7
; a delay control circuit
3
for controlling a delayed value of a ring oscillator on the basis of information from the frequency comparator circuit
2
; the ring oscillator
4
comprising a delay variable circuit
5
and an inverter
6
, which are capable of changing the delayed value on the basis of control information from the delay control circuit
3
; and the 1/N divider
7
for dividing an output clock signal of the ring oscillator by N.
The frequency comparator circuit
2
counts the numbers of pulses of two input clock signals from the 1/M divider
1
and the 1/N divider
7
, by means of a counter, and compares the frequencies of the two clock signals on the basis of magnitude of the counted numbers. The delay control circuit
3
controls the delayed value of the ring oscillator
4
on the basis of information of the frequency comparator circuit
2
so that the clock frequency of the ring oscillator
4
divided by N is equal to the clock frequency obtained by dividing the frequency clock frequency by M.
However, in the conventional digital PLL circuit, there is a problem in that it is difficult to increase a multiplication factor.
For example, it is assumed that the reference clock signal has a frequency of 32 KHz, and the digital PLL output clock signal has a frequency of 32 MHz, the multiplication factor being 1000, the dividing value M of the divider
2
being 1, and the dividing value N of the divider
7
being 1000. Usually, the frequency comparator circuit
2
can not accurately compare frequencies unless a counter of at least 10 bits counts 1000. On the other hand, when the number of counted pulses of the digital PLL output clock signal is 1000, the number of counted pulses of the input clock signal to the frequency comparator circuit
2
from the 1/N divider
7
is 1. Therefore, one comparing operation can not be carried out unless the number of counted pulses of the digital PLL output clock signal is 1000000(=1000×1000).
Thus, the frequency comparison needs such a large counted value. Therefore, in the conventional circuit, which can compare frequencies only one time per about 1000000 counts, there is a problem in that the speed of response is too slow so that jitters are increased, since the frequency of the stable ring oscillator fluctuates in accordance with external voltage, temperature and so forth. In addition, in the lock-in time to lock the PLL circuit, it is required to compare frequencies at least ten times, so that it takes at least few seconds. Therefore, there is also a problem in that it is not allowable.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a clock multiplier circuit for generating a high frequency clock signal having a large multiplication factor from a low frequency input clock, the clock multiplier circuit being capable of comparing frequencies at high speed, the clock multiplier circuit being stable and having a short lock-in time and small jitters.
In order to accomplish the aforementioned and other objects, according to a first aspect of the present invention, a clock multiplier circuit comprises: a counter for counting the number of pulses of a predetermined output clock signal; an expected value generating circuit for generating an expected value for the number of pulses of the predetermined output clock signal per a first period which is sufficiently longer than one period of the predetermined output clock signal; a comparator circuit for comparing the counted value of the counter with the expected value per the first period to output a comparative information on the comparative result; a delay control circuit for generating a delay control signal indicative of change of the frequency of the predetermined output signal in accordance with the comparative information; and an output clock signal generating circuit for generating the predetermined output clock signal while changing the frequency in accordance with the delay control signal.
With this construction, the counted value is compared with the expected value, and the period for comparison between the counted value and the expected value can be far shorter than the period for the frequency comparison in the conventional PLL circuit, so that the lock-in time can be considerably shortened. As a result, a high frequency output clock signal, which is stable and which has small jitters, can be generated at high speed.
In the clock multiplier circuit according to the first aspect of the present invention, the counter may be reset every the first period.
According to a second aspect of the present invention, a clock multiplier circuit comprises: a counter for counting the number of pulses of a predetermine output clock signal; a register for receiving and outputting a counted value of the counter every a first period which is sufficiently longer than one period of the predetermined output clock signal; an expected value generating circuit for generating an expected value for the number of pulses of the predetermined output clock signal per the first period; an accumulated expected value generating circuit for outputting an accumulated expected value, which is obtained by accumulating the expected value, every the first period; a comparator circuit for comparing the counted value outputted from the register with the accumulated expected value to output a comparative information on the comparative result; a delay control circuit for generating a delay control signal indicative of change of the frequency of the predetermined output signal in accordance with the comparative information; and an output clock signal generating circuit for generating the predetermined output clock signal while changing the frequency in accordance with the delay control signal.
With this construction, the counter continues to count up without being reset every one period for comparison in the comparator. The expected value for the counted value is accumulated to be an accumulated expected value which is twice as large as the expected value in one period for comparison when the second frequency comparison is carried out, three times as large as the expected value in one period for comparison when the third frequency comparison is carried out, and L times as large as the expected value in one period for comparison when the number L frequency comparison is carried out. Then, the counted value is compared with the accumulated expected value. Therefore, the frequency error can be very small in a period T which is sufficiently longer than one period of the input clock signal. As a result, a high frequency output clock signal, which is stable and which has small jitters, can be generated at high speed.
In the clock multiplier circuit according to the second aspect of the present invention, the counter, the register and the accumulated expected value generating circuit may be reset per a second period which is sufficiently longer than the first period.
In addition, in the clock multiplier circuit according to the first or second aspect of the present invention, the comparator circuit may be a subtracter circuit.
Moreover, the output clock signal generating circuit may comprise: a plural stages of delay generating circuits, the number of stages of the delay generating circuits to be connected in serie

Affiliated with

Also associated with

Rating

Clock multiplier circuit capable of generating a high... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock multiplier circuit capable of generating a high..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock multiplier circuit capable of generating a high... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2568024