Clock multiplier

Details Clock multiplier Clock multiplier

1995-12-04

1998-07-21

Coles, Sr., Edward L.

395109, 395107, G06K 1500

Patent

active

057845433

ABSTRACT:
The clock multiplier which is useful for multiplying the frequency of a clock signal by an integer factor, like 4 or 6. In a typical application this multiplier is used for achieving high addressability printing on a laser printer. In order to print at a quarter pixel resolution, the frequency of the clock signal must be multiplied by four. It is important that at the beginning of the pulse train, as occurs on the leading edge of each scanline, the new clock locks in at once with the input clock from the printer. The clock multiplier, as described below, has capabilities for multiplying the input clock by a factor of 4. Other factors, like 2, 6 or 8 can easily be achieved by expanding on the description. The circuit features automatic and instant locking to the input pulse train, as well as automatic tuning to the present clock frequency.

REFERENCES:
patent: 4841551 (1989-06-01), Avaneas
patent: 4908842 (1990-03-01), Collins
patent: 4955040 (1990-09-01), Sarkoezi
patent: 5022057 (1991-06-01), Nishi et al.
patent: 5243441 (1993-09-01), Kawata
patent: 5274472 (1993-12-01), Williams
patent: 5387985 (1995-02-01), Loce et al.
patent: 5495341 (1996-02-01), Kawana et al.
patent: 5606648 (1997-02-01), Walther et al.

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