Clock monitor circuit and method

Details Clock monitor circuit and method Clock monitor circuit and method

1983-11-17

1986-12-30

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307517, 307234, 307246, 328120, H03K 513, H03K 519, H03K 1756

Patent

active

046330976

ABSTRACT:
A clock monitor circuit and method for providing an indication at the output thereof of the presence of an input clocking signal. If the clock input is operating properly, two charge storage nodes will be charged and the output of the circuit will be high. If the clock input is stuck, the output of the clock monitor circuit will be low.

REFERENCES:
patent: 3233118 (1966-02-01), Jensen
patent: 3582676 (1971-06-01), Rosenbaum
patent: 3624410 (1971-11-01), Bruckert
patent: 4197508 (1980-04-01), Takaoka
patent: 4322642 (1982-03-01), Sugasawa
patent: 4345209 (1982-08-01), Walker

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