Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2001-02-01
2002-05-21
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S263000
Reexamination Certificate
active
06392461
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock modulator for use in reducing electromagnetic wave interference (ElectroMagnetic Interference; EMI), and particularly to a clock modulator suitably used for an in-vehicle electronic equipment requiring an EMI countermeasure.
2. Description of the Related Art
In recent years, an LSI substrate on which an LSI (Large Scale Integrated Circuit) operating in synchronization with a clock, such as a microcomputer or an ASIC (IC for special use), has been used for various devices. For example, a car navigation system as an in-vehicle electronic equipment has a built-in LSI substrate on which a microcomputer or an ASIC operating at a fundamental clock frequency of several tens MHz is mounted. However, since a harmonic component of the fundamental clock frequency of a clock pulse for operating the microcomputer or the ASIC overlaps with a frequency of an FM band (66 MHz to 108 MHz) used in an in-vehicle radio, in order to keep the quality of the in-vehicle radio, it becomes necessary to take an EMI countermeasure to reduce undesired radiation noise of the harmonic component.
As a method of the EMI countermeasure, there is a method in which with respect to a frequency spectrum of a fundamental clock pulse, a fundamental frequency and its harmonic component are respectively made center frequencies, and respective spectra are dispersed to both sides of the respective center frequencies with the elapse of time, so that the level of the undesired radiation noise is reduced.
The dispersion of a spectrum can be obtained by continuously phase modulating a fundamental clock pulse. For example, U.S. Pat. No. 5,442,664 discloses a phase modulation clock pulse generator set forth below.
A modulator for the phase modulation clock pulse generator receives clock pulses exhibiting a reference phase from a clock pulse source. A delay circuit is connected to the clock pulse source, and this delay circuit includes n tap connections. Each of the tap connections provides a clock pulse that is delayed by a different phase delay from the reference phase. A multiplexer is connected to each of the n tap connections, and this multiplexer provides an output manifesting the clock pulses. A selector circuit controls the multiplexer to sequentially connect any sequence of different ones of the n tap connections to the multiplexer's output, whereby the output manifests a series of clock pulses which have different phase displacements from the reference phase.
By using this sort of phase modulation clock pulse generator, phase modulated clock pulses can be obtained, and it becomes possible to reduce the undesired radiation noise by the spectral dispersion. Meanwhile, if the dispersion number of the spectrum of each frequency is increased, the circuit scale of a circuit used for the EMI countermeasure is enlarged. On this account, there occurs a problem that it is impossible to avoid an increase in a circuit area of an LSI substrate in which the EMI countermeasure is taken and an increase in the cost thereof.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a clock modulator which can reduce undesired radiation noise by a low spectral dispersion number.
The above object is achieved by a clock modulator comprising a delay circuit in which delay elements of plural stages are connected in series with each other, each outputting an output pulse delayed from an input pulse by a phase delay time &tgr;, and a selection circuit for sequentially selecting the output pulse outputted from each of the delay elements of the plural stages, and the clock modulator is characterized in that with respect to a fundamental clock pulse inputted to the delay element of the first stage, a phase variation amount of the output pulse from the delay element of the first stage and a phase variation amount of the output pulse from the delay element of a final stage are near ±45° when a phase of the output pulse from the delay element at a center position of the delay elements of the plural stages is made a reference.
In the structure of the present invention, the output pulses are sequentially selected by repeating ascending order and descending order operations, so that the spectral dispersion of dispersion number
2
is obtained. As shown in
FIG. 3
of the present embodiment, if the phase variation amount of the output pulse from the delay element of the first stage and the phase variation amount of the output pulse from the delay element of the final stage are near ±45° when the phase of the output pulse from the delay element at the center position of the delay elements of the plural stages is made the reference, the maximum noise reduction effect in the FM band can be obtained. The above clock modulator of the present invention is characterized in that the phase delay time &tgr; is set to about 0.8% of a period of the fundamental clock pulse.
Like the structure of the present invention, when the phase delay time &tgr; is set to about 0.8% of the period of the fundamental clock pulse, as shown in
FIG. 2
of the present embodiment, the maximum noise reduction effect in the FM band can be obtained.
The clock modulator of the present invention is characterized by comprising a power supply voltage control portion for controlling power supply voltage applied to the delay elements of the respective stages. Besides, it is characterized in that the power supply voltage control portion comprises a D/A converter.
According to the structure of the present invention, in the case where a clock of a relatively low frequency is inputted, power supply voltage applied to the respective delay elements is lowered by the power supply voltage control portion to prolong the phase delay time &tgr; of the respective delay elements, and in the case where a clock of a high frequency is inputted, the applied voltage is raised to shorten the phase delay time &tgr; of the respective delay elements. By this, irrespective of the fundamental clock frequency, the phase delay time &tgr; of the respective delay elements can be set to about 0.8% of the period of the fundamental clock pulse.
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patent: 5719515 (1998-02-01), Danger
patent: 5796673 (1998-08-01), Foss et al.
patent: 5936678 (1999-08-01), Hirashima
patent: 5945862 (1999-08-01), Donnelly et al.
patent: 5994938 (1999-11-01), Lesmeister
patent: 6100735 (2000-04-01), Lu
patent: 6104223 (2000-08-01), Chapman et al.
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patent: 6229364 (2001-05-01), Dortu et al.
Emi Naoto
Morishita Tomonari
Nunokawa Hideo
Fujitsu Limited
Nguyen Linh
Tran Toan
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