Clock modulating circuit

Details Clock modulating circuit Clock modulating circuit

2002-11-26

2004-11-23

Mis, David (Department: 2817)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S291000, C327S293000, C327S299000

Reexamination Certificate

active

06822499

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock modulating circuit which is used in a clock input such as a microcontroller unit (hereinafter called “MCU”) or the like and reduces radiant noise synchronized with an original oscillation frequency.
2. Description of the Related Art
An MCU has been widely used in various control of a vehicle. With the speeding up of the MCU in recent years, radiant noise generated from the MCU is superimposed on an FM frequency band and exerts a bad influence on a car radio or the like. As one countermeasure against it, there has been used a method of modulating an original oscillation clock and dispersing radiant noise generated in synchronism with an original oscillation frequency (e.g., Japanese Patent Application Laid-Open No. Sho 62(1987)-63327, etc.).
Japanese Patent Application Laid-Open No. Sho 62(1987)-63327 has disclosed the following method. Since a specific harmonic is generated as noise when the frequency of a fundamental wave fo is fixed to a constant value, the frequency of the fundamental wave fo is modulated at random within a range that exerts no influence on the control accuracy of an MCU. Further, a high-frequency spectrum is dispersed to reduce respective crest values. The influence of the high-frequency noise on the outside is reduced in this way. The frequency of the fundamental wave fo is modulated on a random number basis in a read/write cycle of the MCU. A circuit for modulating the original oscillation clock is made up of a delay circuit having a plurality of delay elements connected in series and switches for respectively selecting any of the delay elements every pulses.
A pulse of the original oscillation clock is supplied from the delay element selected from the plurality of delay elements by the corresponding switch. This switch is controlled by a shift register constructed using a plurality of flip-flop circuits. The selected delay element varies for each pulse of the original oscillation clock and a plurality of the switches are turned ON in order. The rising edges of outputted pulses are modulated so that a high-frequency spectrum is dispersed.
In the conventional method, however, the rising edge of each pulse of the original oscillation clock is modulated, whereas the falling edge thereof remains fixed. Therefore, the conventional method is accompanied by a problem that when a circuit synchronized with the rising edge of the clock and a circuit synchronized with the falling edge of the clock exist in the MCU or the like in mixed form, the effect of reducing radiant noise is degraded. This is because no radiant noise is dispersed in the circuit synchronized with the falling edge thereof.
In the conventional method as well, the ratio between an “H” interval and an “L” interval of a modulated clock, i.e., a duty ratio changes. Therefore, a problem arises in that the conventional method cannot be applied to an MCU including a circuit dependent on a duty ratio, e.g., a circuit having no margin during an “H” interval of a clock, etc.
SUMMARY OF THE INVENTION
The present invention may provide a clock modulating circuit which does not degrade the effect of reducing radiant noise even where a circuit synchronized with the rising edge of a clock and a circuit synchronized with the falling edge of the clock exist in mixed form.
Further, the present invention may provide a clock modulating circuit applicable even to an MCU or the like including a circuit dependent on a duty ratio.
A clock modulating circuit of the present invention includes a first to nth delay circuits, a selection signal generator and a selection circuit. The first delay circuit receives an original clock signal and outputs a delayed clock signal. The second to nth delay circuits receive the delayed signal output from the preceding delay circuit and output delayed clock signals. The selection signal generator outputs a selection signal in response to the original clock signal. The selection signal has an instruction for selecting in ascending order from the first to nth delay circuits and then in descending order from the nth to first delay circuits. The selection circuit is connected to the first to nth delay circuits and the selection signal generator. The selection circuit receives the delayed signals from the first to nth delay circuits and outputs one of the delayed clock signals in response to the selection signal.


REFERENCES:
patent: 6518813 (2003-02-01), Usui
patent: 62-063327 (1987-03-01), None

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