Clock latency compensation circuit for DDR timing

Details Clock latency compensation circuit for DDR timing Clock latency compensation circuit for DDR timing

1998-06-09

2000-08-08

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327158, H03L 706

Patent

active

061007331

ABSTRACT:
A clock latency circuit, method and system is provided which allows the synchronization of data according to the rising and falling edges of a system clock.

REFERENCES:
patent: 4985639 (1991-01-01), Renfrow et al.
patent: 5216302 (1993-06-01), Tanizawa
patent: 5939912 (1999-08-01), Rehm
patent: 5939913 (1999-08-01), Tomita

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