Clock jitter suppressing circuit

Details Clock jitter suppressing circuit Clock jitter suppressing circuit

1990-09-17

1992-04-07

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Counting or dividing in incremental steps

Beam type tube

377 45, 328 55, 307597, 307269, H03K 1716, H03K 5159

Patent

active

051031850

ABSTRACT:
A clock jitter suppressing circuit includes a control circuit, a delay circuit, and a selection circuit. The delay circuit sequentially delays a clock signal at time intervals sufficiently shorter than the period of the clock signal. The selection circuit selects and outputs one of delay outputs from the delay circuit which is determined in accordance with a selection signal. The control circuit generates a selection signal for selecting a predetermined delay output when no jitter is caused in the clock signal. Every time jitter is caused in the clock signal, the control circuit generates a selection signal for selecting a delay output which is shifted by an amount corresponding to the phase amount of the jitter in a direction to cancel a polarity of the jitter.

REFERENCES:
patent: 3983498 (1976-09-01), Malek
patent: 4290022 (1981-09-01), Puckette
patent: 4700347 (1987-10-01), Rettberg et al.
patent: 4713621 (1987-12-01), Nakamura et al.
patent: 4757264 (1988-07-01), Lee et al.
patent: 4812783 (1989-03-01), Honjo et al.
patent: 4868430 (1989-09-01), Stewart

Affiliated with

Also associated with

Rating

Clock jitter suppressing circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock jitter suppressing circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock jitter suppressing circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1898066