Clock invert and select circuit

Details Clock invert and select circuit Clock invert and select circuit

1992-11-25

1994-08-23

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307465, 307269, H03K 19096, H03K 19094

Patent

active

053410483

ABSTRACT:
A system and method for selectively inverting a clock signal. Clock (CLK) and inverted clock (NCLK) signals are generated. A control signal (RCTL) and inverted control signal (NRCTL) operate the clock invert circuit (201). First (C1) and second (C2) output lines are coupled to both of the clock and inverted clock signals, but are selectively connected to one of such signals by way of the control and inverted control signals. According to a preferred aspect of the invention, the control signals are generated with an SRAM bit (207). The clock and inverted clock signals are used in, for example, a programmable logic device such as with a flip-flop (205) clock input.

REFERENCES:
patent: 4613773 (1986-09-01), Koike
patent: 5070257 (1991-12-01), Farwell
patent: 5140174 (1992-08-01), Meier et al.
patent: 5157291 (1992-10-01), Shimoda
patent: 5220217 (1993-06-01), Scarra et al.
Altera Data Book, Sep. 1991, pp. 99-106.

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