Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
2001-01-12
2004-02-24
Nguyen, Linh M. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S231000
Reexamination Certificate
active
06696876
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed at phase control of clock signals. More specifically, the present invention is directed at an apparatus for interpolating phase differing clocks through capacitive weighting.
Often it is desirable to be able to precisely control the phase of the clocks used in a circuit. Generating a controlled phase can be difficult. The generation method should work across a broad range of frequencies and would ideally have a control, either analog or digital, which gives monotonic changes and desirably linear changes in the phase position. Monotonicity and linearity are important when the phase position is controlled as part of a servo loop. If the control is not monotonic the servo loop can erroneously “lock-up” in the non-monotonic regions of the phase transfer curve. If the phase control is not linear, then the servo loop will have varying closed loop behavior (poles, zeros, bandwidth, and stability will vary) and it is more difficult to design the servo loop to be stable over all regions of operation.
Past attempts at phase control have contemplated the use of an interpolating buffer to perform phase interpolation. See, for example, Stefanos Sidiropoulos et al., “A Semidigital Dual Delay-Locked Loop,
IEEE Journal of Solid-State Circuits
, vol. 32, no. 11 (1997), pp. 1683-1692 and C. K. Yang et al., “A 0.8-&mgr;m CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links,”
IEEE Journal of Solid-State Circuits
, vol. 31, no. 12 (1996), pp. 2015-2023. Under this past approach, the outputs of two buffers are tied together and the buffers' inputs are configured to accept two clock signals, which are separated by a phase P. The resulting output clock has a phase somewhere between 0 to P. The clock phase can be made selectable from 0 to P by digital control select signals, which control the relative strengths of the two buffers. The disadvantage of this approach is that the buffers present a nonlinear amplification stage, which amplifies even relatively slow clock edges into sharp current steps. In effect, the RC response time of the buffer outputs averages the two sharp current steps into an interpolated voltage waveform. Moreover, if the clock phase separation P is appreciable, compared to the RC response time of the buffer's outputs, then the interpolation is rather poor and the transfer function can become nonlinear.
SUMMARY OF THE INVENTION
This invention is directed at clock interpolation circuit that uses capacitive weighting of out-of-phase clock inputs to control the phase of an interpolated clock output.
In a first aspect of the invention, a clock interpolation circuit comprises a first capacitor having a first terminal configured to accept a first clock having a first phase and a second terminal coupled to an output node providing an interpolated output clock. A second capacitor having a first terminal is configured to accept a second clock having a second phase and a second terminal coupled to the output node. The phase of the output clock is controlled by the ratio of the capacitance of the first capacitor and the capacitance of the second capacitor. The capacitances in this aspect of the embodiment may be fixed or variable.
In a second aspect of the invention, a clock interpolation circuit comprises a first plurality of capacitors coupled to an output node of the circuit and selectively coupled in parallel; a first plurality of switches coupled in series with the first plurality of capacitors, each switch of the first plurality of switches having an open position and a closed position and each switch having a first end coupled to a first clock with a first phase and a second end coupled to a capacitor of the first plurality of capacitors, the first plurality of switches controlled by a plurality of control signals that affect the position of each of the first plurality of switches; a second plurality of capacitors coupled to the output node of the circuit and selectively coupled in parallel; and a second plurality of switches coupled in series with the second plurality of capacitors, each switch of the second plurality of switches having an open position and a closed position and each switch having a first end coupled to a second clock with a second phase and a second end coupled to a capacitor of the second plurality of capacitors, the second plurality of switches controlled by a plurality of control signals that affect the position of each of the second plurality of switches. The output node provides an interpolated output clock having a phase determined by a ratio of a first capacitance of selected capacitors from the first plurality of capacitors and a second capacitance of selected capacitors from the second plurality of capacitors.
In a third aspect of the invention, a clock interpolation circuit comprises a first plurality of capacitors, first means for selecting a first number of capacitors from the first plurality of capacitors so that the first number of capacitors are coupled in parallel and have a first terminal coupled to a first clock having a first phase and a second terminal, a second plurality of capacitors, and second means for selecting a second number of capacitors from the second plurality of capacitors so that the second number of capacitors are coupled in parallel and have a first terminal coupled to a second clock having a first phase and a second terminal coupled to the second terminal of the first number of capacitors. In this aspect of the invention, the interpolation circuit provides an interpolated output clock having a phase determined by a ratio of a capacitance of the first number of capacitors and the second number of capacitors.
In a fourth aspect of the invention, clock interpolation circuit comprises a plurality of capacitors, each capacitor having a first terminal configured to accept a corresponding plurality of clocks of different phases and each capacitor having a second terminal coupled to an output node of the circuit. The output of the clock interpolation circuit provides an interpolated clock having a phase determined by a ratio of the plurality of capacitors.
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.
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Chih -Kong Ken Yang, et al., “A 0.8-&mgr;m CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links,”IEEE Journal of Solid-State Circuits, vol. 31, No. 12, pp. 2015-2023, (Dec. 1996).
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Bosnyak Robert J.
Drost Robert J.
Nguyen Linh M.
Sun Microsystems Inc.
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