Clock input filter circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By pulse width or spacing

Reexamination Certificate

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Details

C327S175000, C327S291000, C327S299000

Reexamination Certificate

active

07411427

ABSTRACT:
A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.

REFERENCES:
patent: 3566038 (1971-02-01), Slavin
patent: 3585307 (1971-06-01), Greenberg
patent: 3904894 (1975-09-01), Ciolli
patent: 4355283 (1982-10-01), Ott
patent: 5650739 (1997-07-01), Hui et al.
patent: 5841296 (1998-11-01), Churcher et al.
patent: 6507221 (2003-01-01), La Rosa
patent: 6535057 (2003-03-01), Chakravarthy
patent: 2004/0108878 (2004-06-01), Dosho et al.
patent: 2006/0082391 (2006-04-01), Hsu et al.

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