Clock input buffer with noise suppression

Details Clock input buffer with noise suppression Clock input buffer with noise suppression

1999-09-07

2001-12-11

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Delay controlled switch

C327S394000, C327S291000, C327S175000, C327S108000, C326S121000, C326S083000, C326S056000

Reexamination Certificate

active

06329867

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to an integrated circuit and more particularly to an integrated circuit with a clock input buffer circuit.
BACKGROUND OF THE INVENTION
Present complementary metal oxide semiconductor (CMOS) synchronous dynamic random access memory (SDRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. Advances in system technology require ever increasing clock rates and memory bus widths to achieve high data rates. Both of these methods, impose equally demanding limitations on memory testers that must guarantee functionality of the memory circuits under all conditions. Moreover, these memory testers must simultaneously test many of the SDRAM memory circuits in order to meet production quotas. These simultaneous tests, however, impose parasitic loads having substantial capacitance and inductance on drive circuits of the memory tester. Consequently, these parasitic loads greatly slow rise and fall times of test waveforms applied to the memory circuits. In many cases, a slow transition time of these test waveforms may induce internal oscillation of the memory clock and control signals leading to erroneous memory circuit test failures.
A clock input buffer circuit (FIG. 5) of U.S. patent application Ser. No. 09/039,012, filed Mar. 13, 1998, now U.S. Pat. No. 6,023,181, issued Feb. 8, 2000, produces a clock pulse signal IOCLK having a rising edge or transition two gate delays after a rising edge of clock input signal CLK. This rising edge turns off transistors 221 and 227, thereby disabling a first inverter of the two gate delays. Inverter 231 applies an inverted clock pulse signal at an input terminal of delay circuit 235. Delay circuit 235 produces a low output signal after a predetermined delay, thereby turning on transistor 245 and driving terminal 229 high. This high level at the input terminal of inverter 253, the second of the gate delays, drives clock pulse signal IOCLK low again. A significant problem occurs with this clock input buffer circuit, however, when noise on clock input signal CLK causes a subsequent low-high-low transition. This low-high-low transition propagates directly through the clock input buffer circuit to clock pulse signal IOCLK, since the clock input buffer is immediately enabled by a falling edge of clock input signal CLK. This false transition causes erroneous memory circuit test failure when internal operation of the memory circuit is no longer synchronized with the memory tester.
SUMMARY OF THE INVENTION
These problems are resolved by a circuit, comprising a delay circuit coupled to receive a clock input signal and a control signal. The control signal has a first logic state and a second logic state. The delay circuit produces a clock control signal at a first time in response to the first logic state and at a second time in response to the second logic state. A clock circuit is coupled to receive the clock input signal and is enabled by the clock control signal. The clock circuit produces a clock pulse signal having a predetermined width in response to a transition of the clock input signal.
The present invention provides minimal delay between the clock input signal and the first clock pulse signal. Erroneous clock pulse signals are precluded by the clock control signal.


REFERENCES:
patent: 3914702 (1975-10-01), GehWeiler
patent: 4758737 (1988-07-01), Hirano
patent: 4825106 (1989-04-01), Tipon et al.
patent: 5065054 (1991-11-01), Nguyen et al.
patent: 5517133 (1996-05-01), Sandhu
patent: 5541528 (1996-07-01), Montoye et al.
patent: 5550499 (1996-08-01), Eitrheim
patent: 5633607 (1997-05-01), Millar
patent: 5808486 (1998-09-01), Smiley
patent: 5886562 (1999-03-01), Garrity et al.
patent: 5955893 (1999-09-01), Chang et al.
patent: 6005432 (1999-12-01), Guo et al.
patent: 6023177 (2000-02-01), Kim et al.
patent: 6023181 (2000-02-01), Penney et al.
patent: 6094080 (2000-07-01), Jeong et al.

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