Clock input buffer with increased noise immunity

Details Clock input buffer with increased noise immunity Clock input buffer with increased noise immunity

1999-03-18

2002-06-18

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S294000, C327S379000, C327S389000

Reexamination Certificate

active

06407608

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor device signal buffer circuits, and more particularly to clock buffer circuits for a semiconductor device.
BACKGROUND OF THE INVENTION
Many electronic systems are operated according to a system clock, which coordinates rapid operations between different semiconductor devices within the system. Data and commands can be transferred according to the clock signal allowing for rapid and efficient use of command and data bus lines. Semiconductor devices that function according to an external system clock are often referred to as synchronous devices, as their operation is synchronous with the system clock.
One type of synchronous semiconductor device is a synchronous random access memory (RAM). In many synchronous RAMs, data and command inputs are latched on the rising edge of the system clock signal. Similarly, synchronous RAMs typically latch input data, or provide output data in synchronism with the system clock. In order to ensure accurate timing of such operations, it is important that the synchronous RAM be able to receive the system clock signal, and distribute it to internal control and timing circuits, including input latches and output buffers.
Synchronous RAMs often include a clock buffer circuit for receiving the system clock signal and increasing its strength for use by other circuits within the synchronous RAM. A common buffer arrangement includes one or more inverter circuits arranged in series, that receive the system clock signal as an input, and provide the buffered clock as an output. A drawback to utilizing conventional inverter arrangements in synchronous semiconductor devices is the susceptibility of such circuits to noise. When a system is operating, the other circuits of the system may introduce noise into the system clock signal. A conventional buffer circuit can allow the noise to propagate through the buffer and into the circuits within. Noise on the falling edge of the clock signal can be interpreted incorrectly as a rising clock edge by internal circuits. This can result in an invalid command or address being latched by the synchronous RAM, output data being provided at an incorrect time.
The effects of noise on a system clock can be reduced by utilizing hysteresis. Hysteresis raises the level at which a rising clock transition will be detected, and/or lowers the threshold at which a falling clock transition will be detected. In this arrangement, temporary transitions between the hysteresis threshold voltages will not result in a false transition. A drawback to hysteresis is that it results in a delayed clock signal. Such a delay may not be acceptable in high-speed applications, as it lowers the response time of the semiconductor device. Thus, hysteresis may not be suitable for many synchronous RAMs which require very rapid data access times.
It would be desirable to provide a clock buffer circuit that reduces the effect of noise on a signal transition, but does not result in excessive delay in the buffered clock signal.
SUMMARY OF THE INVENTION
According to the preferred embodiment, a clock buffer circuit reduces the adverse effects of noise on the falling edge of a system clock signal by generating a pulse in response to the falling edge. The pulse temporarily enables a boost device within the clock buffer circuit, which strengthens the driving ability of the buffer circuit.
According to one aspect of the preferred embodiment, the pulse generated by the clock buffer circuit has a duration that is less than half of a system clock cycle, and so will not adversely affect the generation of low-to-high transitions in the buffered clock signal.
According to another aspect of the preferred embodiment, the clock buffer circuit includes an enabling circuit for placing the preferred embodiment in the disabled state. To rapidly place nodes within the buffer circuit into a disabled state, the boost device temporarily enabled.
An advantage of the preferred embodiment is that it provides a clock buffer circuit with increased noise immunity in which the speed of the buffered clock signal is not substantially affected.


REFERENCES:
patent: 4498021 (1985-02-01), Uya
patent: 6023181 (2000-02-01), Penny et al.
patent: 6023182 (2000-02-01), Milshtein et al.
patent: 5-22106 (1993-01-01), None

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