Clock generators having programmable fractional frequency divisi

Details Clock generators having programmable fractional frequency divisi Clock generators having programmable fractional frequency divisi

1992-04-22

1994-02-15

Mai, Tan V.

Boots, shoes, and leggings

377 47, G06F 752

Patent

active

052872963

ABSTRACT:
A clock generator is described for generating an output clock frequency from an input clock frequency where the frequencies of the clocks are not integrally related. The division process is designed using the quotients of the Euclidean theorem for determining the greatest common divisor of two integers in such a way as to alleviate the adverse effects of jitter. Applications to oversampled sigma-delta codecs are described.

REFERENCES:
patent: 4241408 (1980-12-01), Gross
patent: 4244027 (1981-01-01), Shai
patent: 4413350 (1983-11-01), Bond et al.
patent: 4837721 (1989-06-01), Carmichael et al.
patent: 5052031 (1991-09-01), Malloy
patent: 5088057 (1992-02-01), Amrany et al.
Nussbaumer, Henri J., "Fast Fourier Transform and Convolution Algorithms", Springer-Verlag, 1982, pp. 4-7.

Affiliated with

Also associated with

Rating

Clock generators having programmable fractional frequency divisi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock generators having programmable fractional frequency divisi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock generators having programmable fractional frequency divisi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1212463