Clock generator with reset and initialization circuitry

Details Clock generator with reset and initialization circuitry Clock generator with reset and initialization circuitry

1984-11-29

1987-02-03

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 307529, 307265, 307443, 328 63, H03K 3017

Patent

active

046410449

ABSTRACT:
After detecting a leading edge of a stop control signal supplied from an external circuit, an oscillation output signal is cut off at an input side of a frequency divider in synchronism with the first leading edge of a clock signal generated from the frequency divider, thereby stopping the generation of clock signals. The stopping of the clock signal generating operation is released in such a manner that, immediately after a trailing edge of an external control signal is detected, an internal state of the frequency divider is initialized, and the oscillation output signal which has been cut off is supplied to the frequency divider again, thereby generating a proper clock signal.

REFERENCES:
patent: 3997800 (1976-12-01), Bain
patent: 4241418 (1980-12-01), Stanley
patent: 4309662 (1982-01-01), Baudoux
patent: 4329652 (1982-05-01), Higa et al.
patent: 4398155 (1983-08-01), Atwell, Jr. et al.
patent: 4419629 (1983-12-01), O'Brien
patent: 4560939 (1985-12-01), DeKarske et al.
Intel iAPC 86, 88 User's Manual, pp. A-18 to A-20.

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