Clock generator with multiple feedback paths including a delay l

Details Clock generator with multiple feedback paths including a delay l Clock generator with multiple feedback paths including a delay l

1998-05-27

2000-01-11

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327292, 327294, H03L 707

Patent

active

060140488

ABSTRACT:
The present invention encompasses the use of multiple feedback paths in a clock source for an integrated circuit device to maintain phase lock to an external clock. It is further contemplated by the present invention that feedback paths are provided from the internal clock distribution path and from a matching path that approximates the delay of the clock distribution path. The matching path may comprise a delay locked loop. Feedback from the clock distribution path is used in normal operation and feedback from the matching path is used when the internal clock distribution path is disabled. The clock source of the present invention also may implement power management functions.

REFERENCES:
patent: 5173617 (1992-12-01), Alsup et al.
patent: 5428317 (1995-06-01), Sanchez et al.
patent: 5483204 (1996-01-01), Tanoi
Weste, et al, "Principles of CMOS VLSI Design: A Systems Perspective," 2.sup.nd Ed., pp. 334-336, 356-357 and 364, published by Addison-Wesley Publishing Company, 1993.

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